Reduced Dynamic Gate Pulse Stress Instability in Dual Gate a-InGaZnO Thin Film Transistors

The dynamic gate pulse stress effect on the electrical performance of single gate (SG) and dual gate (DG) thin-film transistors (TFTs) is reported. The stress is implemented with rising and falling pulses of 1 and
$0.1 ~\mu \text{s}$
respectively with positive gate pulse (0 to +30V). The DG TFT under slow switching (
$1 ~\mu \text{s}$
) shows stable TFT performance with a small threshold voltage shift (
$\Delta {V}_{\text{TH}}$
) of 1.3 V than SG TFT (
$\Delta {V}_{\text{TH}}$
of 2.4 V) for 24 h stress at room temperature. Under a fast switching of
$0.1 ~\mu \text{s}$
, DG TFT exhibits a 1.8 V shift, and SG TFT shows a 3.0 V shift. The recovery behavior of the transfer curves is also checked by keeping the TFTs unbiased for 24 h after applying stress, resulting in the DG TFTs showing complete recovery while SG TFTs exhibiting partial recovery. The lifetime of DG TFTs is found to be 7.5 times longer than that of SG TFTs under dynamic gate pulse stress.