A Six-input Dynamic Comparator with Low Kickback Noise at Cryogenic Temperature

This paper presents a new two-stage six-input dynamic comparator as the core circuit of the CIFF NS-SAR ADC block. It operates at 4.2 K with
$772\ \mu \mathrm{W}$
power consumption, provides three different gains for the integrating path, and performs the addition operation. The proposed comparator only needs one external clock. Simulation verifications are carried out using a compact cryogenic BSIM3V3 model in SMIC 180 nm CMOS technology. This proposed comparator has more considerable gain and half kickback noise than the previous structures.