A Framework of Embedded Logic Analyzer for FPGA

As modern integrated circuits increase in size and complexity, more and more verification effort is necessary to ensure the correctness of the design. Compared with using software simulation and traditional logic analyzer, using FPGA for prototype verification is a more efficient solution and is being accepted by more and more designers. Embedded logic analyzer (ELA) is an indispensable tool for FPGA debugging. In this paper, we propose an ELA framework, including the software part and the debug core in hardware. In addition, the communication protocol between them is also be discussed emphatically. We focus on solving the problem of complex trigger settings, effectively improving the debugging efficiency of designers.