Dielectric Interface Engineering for High-Performance Monolayer MoS₂ Transistors via hBN Interfacial Layer and Ta Seeding

We developed new dielectric interface engineering approaches in monolayer (1L) MoS
2
transistors. First, hBN encapsulation on the top surface of 1L-MoS
2
unexpectedly minimizes the impact of interfacial trap states in back-gate sweep, leading to the record lowest SS of 62 mV/dec in CVD 1L-MoS
2
back-gated transistors (BG FETs). In addition, hBN-encapsulated transistors show less off-state degradation after Al seeding and top gate dielectric deposition compared to those without hBN encapsulation. Second, to reduce active trap states after the top-gate stack fabrication, we successfully moved the defect band out of the operation window of the MoS
2
Fermi-level by introducing a new seeding layer: Ta. The Ta seeding layer (TaO
x
) can also act as an efficient doping layer. The highest I
ON
of $861 \mu \mathrm{A}/ \mu \mathrm{m}$ at $V_{DS} =1.5\mathrm{V}$ and the lowest SS down to 72 mV/dec in a double-gate (DG) configuration are reported. The contact resistance, R
C
can also reach as low as $230 \Omega \cdot \mu \mathrm{m}$. Our reported $SS, I_{ON}$, and R
C
are among the best reported MoS
2
devices and are on par with those of Si N-type transistors. For low power applications, our devices exhibit record high I
ON
of $598 \mu \mathrm{A}/ \mu \mathrm{m}$ at $V_{DS} =0.65\mathrm{V}$, exceeding IRDS 2028 HD spec. The new dielectric engineering approaches demonstrated in this study could pave the way for realizing high-performance logic devices based on 2D materials.