Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.