18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

We successfully developed new devices and new features in the 18nm FDSOI technology for addressing the low power and the low leakage demands of Micro-Controller Units (MCUs). In a quadruple fully mixable Vt offer, 80% speed enhancement and 2x leakage reduction are demonstrated at $0.6 V V_{dd}$ vs the fastest and vs the less-leaky 28nm FDSOI devices, respectively. Low leakage device options have been built for all device families of this Triple Gate Oxide (TGO) platform (i.e thin: SG – medium: EG – thick: eZG), achieving 10pA/μ m for SG/EG transistors and 1pA/μm Idoff for 3.3V eZG ones without adding any mask nor process cost. For SRAM, the high-density $0.102 \mu m^{2}$ SRAM bitcell has been carefully optimized and, in addition, an innovative Zero-power $0.532 \mu m^{2}$ SRAM (ZpSRAM) is proposed for the first time. As a result, record-low retention leakage of 0.6pA/cell and 30fA/cell are reported respectively for those two bitcells, completing the list of benefits brought to the 18nm FDSOI device suite to fulfill ULP/ULL design requirements.