Mitigating Impact of Defects On Performance with Classical Device Engineering of Scaled Si/SiGe Qubit Arrays

We model an impact on quantum buried Si/SiGe channel devices from a low ~ 1e11 cm
^-2
level of defect densities on semiconductor/dielectric interfaces. We discuss a limitation that spurious dot formation sets on qubit gate operations and the impact of defects on voltage-dependent noise and two-qubit (2Q) gate fidelity. We show that classical device engineering schemes via scaling pitch, dielectric thickness, using deeper SiGe buffers, and screening gates allow to mitigate the impact of defects on quantum performance.