Analysis of Single-Event Upsets and Transients in 22 nm Fully Depleted Silicon-On-Insulator Logic

In this work, single-event upset (SEU) and single-event transient (SET) responses of digital logic in a planar 22 nm conventional-well fully depleted silicon-on-insulator (FD-SOI) technology under various test conditions are presented. The D-flip-flop (DFF) shift registers used for the SEU experiments are more sensitive to upsets when data are dynamically loaded in during irradiation rather than statically stored beforehand, but the clock rate used to load the data does not affect the upset cross sections in any significant way. The digital pattern loaded also affects the upset cross sections, but which cross section is greater between patterns of all “1s” and all “0s” is observed to be opposite for dynamic and static tests. A key capability of the technology studied in this work is the ability to apply biases to the back gates of transistors to alter threshold voltage. For conventional-well designs, as in this work, reverse body bias can be applied, increasing the threshold voltage and decreasing leakage current. Analyzing the effects of applying a back-gate bias on SEU cross section reveals no clear trend for SEU cross sections in the DFF shift registers but applying back-gate bias decreased the SET cross sections measured from an inverter chain by as much as an order of magnitude. Supplementary SPICE-level simulations suggest that the drastic decrease in SET cross section results from attenuation in the inverter chain. The presented experimental and simulation results indicate relatively small single-event cross sections compared to other technologies reported in the literature.