The Circuit Technique for Reducing the Zero Level of the JFET Op-Amp on the Push-Pull Folded-Cascode

In the paper, the authors describe the improved operational amplifier architecture (op-amp). Complementary FETs with the p-n-junction control were used in the design of this op-amp, depletion-mode complementary MOS can also be used. The character of the suggested op-amp is to create conditions that contribute to obtaining low systematical constituent offset voltage (V
off
), which significantly depends on the change in the drain-gate specifications of transistors when the static voltages on their drains change. It should be noted that the high symmetric of the static regimen of the input transistors and output transistors of the folded-cascode of the suggested op-amp is supplied to reduce this constituent V
off
in the considered op-amp circuit. Computer modelling of the op-amp carried out in the LTSpice was fulfilled in the large range of temperatures (from -197°C to 27°C). The suggested circuit design minimizes the systematical constituent V
off
(below 30 µV) and increases the open-loop gain of op-amp to 60 dB. The JFET op-amp circuitry suggested in the paper is advised to analog-to-digital and analog interfaces, incl. those operating at exposure to radiation and low temperatures.