A 14-Gb/s VCSEL Driver in 65-nm CMOS With a Power-Efficient Driving Structure for Particle Physics Experiments

This article presents the design and test results of a 14-Gb/s vertical-cavity surface-emitting laser (VCSEL) driving ASIC based on a commercial 65-nm CMOS technology with a novel power-efficient driving structure. This VCSEL driver consists of an input equalizer stage, a predriver stage, an output driver stage, and their bias circuits. The equalizer stage uses the continuous time linear equalizer (CTLE) structure to compensate for the high-frequency attenuation. The predriver stage is composed of two-stage limiting amplifiers with a shared inductor structure. The proposed output driver stage adopts a novel complementary-modulated method to fully utilize the currents in both branches of the conventional differential structure. In addition, a self-adjusting CTLE preemphasis with an edge peaking function is combined in the output stage to improve the bandwidth and boost the falling edge of the output current signal. This VCSEL driving ASIC has been fully tested with a real VCSEL load, and the wide-open optical eye diagrams have been captured at a 14-Gb/s data rate with a power consumption of 44 mW. The peak-to-peak jitter of the 14-Gb/s optical eye diagram is 15.8 ps with a random jitter of 3.02 ps.