A Hardware Implementation for Deep Reinforcement Learning Machine

Deep Reinforcement Learning (DRL) algorithm is used in many areas of life where an agent learns how to interact with the environment to achieve a certain goal. The Deep Q-Network (DQN) has become a benchmark and building point for many DRL researchers. The DQN maps input states to (action, Q-value) pairs. In this paper, we propose a hardware architecture to implement the DQN algorithm, suitable for real-time applications. Its main features are low power and suitable for limited hardware resources. We have implemented the design on Xilinx Virtex 7 (XC7VX485tffg1927-1) with a Mountain Car simulation environment. Performance results are evaluated in terms of hardware resources, frequency, and power consumption with other reinforcement learning algorithms. Our work has been processed at 131MHz, the neural is 2x24x24x3 and the power consumption is 0.921 w.