An Improved Hybrid LDPC Decoder over Rayleigh Fading Channel

Soft decision decoders applicable to low density parity check codes such as sum product algorithms provide excellent error performance, however, it comes at the expense of computational complexity. Additionally, many iterations may be required of these decoders to achieve desired error performance. The processing delay associated with too many iterations may be a drawback for cases where low latency is a critical requirement. Conversely, performance of hard decision decoders such as bit flipping decoder and its variants, while improved, generally are not on par with that of soft decision decoders. Such decoders also require many iterations to achieve a given error performance. We have proposed a two-stage hybrid decoder with a simplified sum product algorithm (SPA) in the first stage, and an improved noisy gradient decent bit flipping decoder in the second stage. We have shown that our proposed hybrid decoder outperforms the legacy individual decoders, studied in this paper, from error performance point of view as well as required number of iterations that will reduce the overall network latency.