Parasitic effect analysis on TSV design factors

With facing the limit of Moore's law, semiconductor packaging is getting more important. TSV is attracting for next generation packaging technology with advantages such as shorter interconnection length, less transmission delay and faster communication speed. However, as the packaging scale is reduced, it is becoming important to control the performance degradation due to parasitic elements in the TSV array structure. In this paper, parasitic capacitance was simulated using commercial FEA tool based on design of experiment. As a result, it was found that among the three factors, size, aspect ratio, and pitch had the greatest influence in the order. Also, size interacted with other factors, yet there was no significant interaction between pitch and aspect ratio.