Board Level Life Assessment of Large Body Flip Chip Packages with Smaller Solder ball pitch & Methodologies to improve Board level Reliability

Continuously expanding flip chip package market is driven by Data Centre applications, 5G wireless, network devices, healthcare, industrial, vision and automotive applications. The demand for high performance, low power, small form factor, more IOs in a small real estate, smaller bump & solder ball pitches, high layer count substrates is posing engineering challenges to contain package warpage and at the same time to improve working life of packages in end user applications. In this context, one critical part for the overall reliability of packages is the performance of Package to Board solder joints under thermal mechanical stresses. For board level reliability assessment, design of experiment was done using test vehicles using Flip chip package with 7nm silicon device. Test packages were assembled using flip chip assembly process using a multilayer substrate. Assembled packages were mounted on Printed Circuit boards with lead free reflow profile. Board level thermal cycling was done using a thermal cycling chamber. This paper discusses the Design of Experiments, experiment set up, layout of packages on the board, characteristics life using Weibull model, board level life assessment and methodologies to enhance board level solder joint performance