Comprehensive study on effect of chip layout and mold thickness on die shift and warpage for FOWLP applications

There has been an increase in demand for using GaN device for RF power applications especially for 5G and radar applications. The assembly process for GaN devices are done mainly using wirebonding process [1]. However in the recent years, there are many publications presenting on the advantages of using Fan-out WLP packaging for GaN devices. Some of the advantages of using FOWLP packaging are good electrical performance, small package form factor, low assembly cost and easier fabrication process [2]. In this paper, a comprehensive process evaluation coupled with wafer level warpage modelling is evaluated on to study the effect of chip layout, chip thickness, mold thickness on die shift and molded wafer warpage on wafer reconfiguration and RDL process, feasibility of the FOWLP integration flow. The different bonding parameters on wafer reconfiguration, die placement compensation and wafer level mold process needs to be evaluated to achieve minimum placement accuracy and die protrusion of
$\pm 15\mu\mathrm{m}$
.