Determining the Zero-Temperature-Coefficient Point From Device Simulation to Circuit for Improving Temperature Variation Immunity

Thermal issue emerges as one of the critical reliability concerns in integrated circuit design, especially for advanced technology. To improve the temperature immunity and reduce the thermal-related timing guard bands in digital circuits, in this work, we offer a new insight into the zero-temperature-coefficient (ZTC) based design strategy featuring minimizing the temperature-induced delay variation. An effective current-based method to facilitate the ZTC point ( ${V}_{\text {ZTC}}$ ) determination for standard cells is developed, which is demonstrated on advanced gate-all-around (GAA) nanosheet (NS) FETs from 300 to 425 K using the calibrated TCAD simulation. The ${V}_{\text {ZTC}}$ dependencies on the signal input slew rate, output capacitance, and self-heating effects (SHEs) are further investigated from the perspective of the effective current by tracing the voltage trajectory. The mixed-mode TCAD simulation results show that the frequency variation of ring oscillator (RO) reduces nearly ten times when operating near ${V}_{\text {ZTC}}$ and great power-performance trade-offs can also be achieved. The ${V}_{\text {ZTC}}$ determination for standard cells combined with the compensation effect among different standard cells benefits selecting the optimal zero-temperature-delay (ZTD) point in the target path, thereby helping to implement a robust digital design against temperature variation.