A 12-Bit 100MSps Asynchronous SAR ADC with Improved Split Capacitive DAC

This paper describes a 12-bit I00MS/s successive approximation register (SAR) analog-to-digital converter (ADC) and an improved split-capacitor digital-to-analog converter (DAC). The DAC adopts a two-stage structure bridged by unit capacitors, and the high fifth-order capacitors are equally divided. A control scheme combining splitting and monotony is adopted. This scheme can reduce power consumption and optimize the stability time of DAC without introducing common-mode reference voltage (Vcm). The ADC is fabricated using a 65nm CMOS process. The simulation results show that at 1. 2V supply voltage, the SNDR is 65. 4dB, the SFDR is 74. 7dB, and the power consumption is 4. SmW. The ADC core circuit size is 210um*180um, and the FoM is 31. 6fJ/Conv-step at Nyquist input frequency.