A 10-bit 50-MS/s SAR ADC with Binary-Scaled Recombination Weighting Capacitor Array

A 10-bit 50MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in TSMC 65nm CMOS process with a 1.2-V supply voltage. The DAC capacitor array combines the split monotone control scheme with the monotone control scheme to reduce the offset of the comparator due to the variation of the common-mode input voltage. The DAC structure combined with the binary redundancy recombination method can introduce redundancy to calibrate the errors in the quantization process, reduce the overall quantization time, improve the quantization speed and accuracy. Simulation results show that the SAR ADC achieves 53.36 SNDR and 8.57b ENOB at the input signal of 24.21875 MHz and the sampling rate of 50 MS/s, and consumes 2.72 mW of power.