Track-and-Hold Techniques for Ultra High Speed Time-Interleaved ADCs

A hierarchical time-interleaved (TI) track-and-hold (T&H) circuit for an ultra high speed analog-to-digital converter (ADC) is presented. The circuit is designed as a frontend for an 8b32GS/s16-way time-interleaved analog-to-digital converters (ADCs) using a 40nm CMOS process. The input and output buffers of the sampled signals are designed in response to the demand of time-interleaving, and the output buffer is a PMOS source-following structure with common mode compensation in order to balance the requirements of bandwidth and common mode. The circuit has an ENOB of S.77 bits and an SFDR of 55.86 dB at the Nyquist input frequency.