A Mismatch Error Calibration Method for 14-bit 500MS/s Time-interleaved Charge-Domain ADC

A mix-signal type high precision mismatch error calibration method for time-interleaved ADCs is proposed. The calibration method calibrates the clock skew mismatch error based on binary search algorithm. Based on the proposed calibration method, a 14-bit 500MS/s ADC is designed and realized in a 1P6M 0.18 $\mu$m CMOS process. Test results show the 14-bit 500MS/s ADC achieves the SNR of 69.8dBFS and the SFDR of 82.3dB, with 72.1MHz input at 500MS/s, while consumes the power consumption of 365mW.