Design of a 5MHz 4A Half Bridge Gate Driver in 180nm BCD Process for GaN HEMT

A half-bridge gate driver for enhanced-mode GaN HEMT is designed. In order to improve the speed, a new high voltage level-shift circuit is designed. The level-shift circuit uses a variety of strategies to reduce transmission delay, including a common-mode noise cancellation circuit and a positive feedback interlock circuit without RC filtering. Based on the proposed high voltage level-shift circuit, a 5MHz half-bridge gate driver chip with a current of 4A and an output voltage of 6V is implemented in the 180nm BCD process. The test results show that the prototype gate driver has a rise time of 4.1ns and a fall time of 3. 8ns at 5MHz switching frequency for 3nF load. This meets the gate driver requirements of GaN HEMT.