Research and Implementation of Dynamic Reconfigurable Multi-Standard Oriented Coding Block Partition

The division of the coding unit is the core module of video coding, which significantly impacts compression efficiency and encoding complexity. The coding block partition circuit implemented by special hardware is difficult to meet the requirements of coding block partition under various standards. The change of the standard needs to redesign the hardware circuit, resulting in a long design cycle and high design cost. A fast partition method of multi-standard coding on dynamic reconfigurable array structure is proposed. This method optimizes the algorithm after analyzing the algorithm, reduces the complexity of the algorithm, and is realized by parallel algorithm mapping. Finally, by changing the controller configuration, the multi-standard algorithm switching can be realized on a single processing element group (PEG). Experimental results show that this method can realize flexible switching of multiple coding multi-standards by hardware, and the clock frequency can reach 126MHz.