A Low-Power High-Precision 12Bit SAR ADC

This paper designs a 12-bit 6.67ksps successive approximation analog-to-digital converter (SAR ADC). The sampling and holding circuit uses MOS tube as sampling switch and adopts virtual switch and lower plate sampling to improve sampling accuracy. The comparator adopts a dynamic comparator structure composed of two-stage pre-amplification and latch, which reduces the power consumption of the comparator and improves the speed of the comparator. The DAC module adopts a segmented resistance tree structure, which effectively reduces the design difficulty and improves the accuracy of the DAC module. The design and simulation are based on 0.35$\mu$m BCD process. Under 6.67ksps, the conversation range of ADC is 0-2.56V, the power consumption is 40.59$\mu$A, the DNL is −0.8/+0.4LSB, the SNR is 68.146dB, and the SFDR is 85.781dB, ENOB is 11.027bit.