Adaptive Ramp Generator for CMOS Image Sensor

The system resolution of a CMOS image sensor (CIS) is determined by the resolution of an internal single-slope analog-to-digital(SS ADC) converter. The structure of a single-slope ADC is usually composed of a comparator, a ramp generator, a decoder, and a register. The traditional integrated ramp generator circuit is greatly affected by process, voltage and temperature, which results in low accuracy and poor linearity of the ramp signal. This paper introduces a ramp generator which can adjust the slope adaptively. On the basis of the integral ramp generator, the negative feedback mechanism is achieved by the pulse-width locked loop (PWLL) circuit structure. The designed pulse-width locked loop circuit consists of a phase detector, a charge pump and a pulse width modulator. The DNL of the adaptive ramp generator is −0.00054LSB/+0.00033LSB and the INL is −0.00054LSB/+1.103808LSB, which indicates that the structure can adjust the ramp signal dynamically and improve the anti-PVT capability of the ramp signal. Compared with the ramp generator in the references, the ramp in this paper has the advantages of high accuracy and low power consumption.