Design and Implementation of Dynamic Self-Reconfigurable DCT Transform Unit Supporting Multiple Coding Standards

The implementation of discrete cosine transform (DCT) on dedicated hardware cannot meet the calculation requirements of different residual block sizes in different coding standards. The upgrading of standards requires redesigning DCT unit circuits, resulting in a long design cycle and high design overhead. An implementation method of the DCT transform unit on the dynamic self-reconfigurable array structure driven by a mixed instruction stream and data stream is proposed in this paper. This method is based on the state monitoring mechanism. Monitoring the execution status of the processing element group(PEG) can process in parallel on multiple PEGs and realize the discrete cosine transform supporting various video coding standards on a single platform. The experimental results show that 16 / 8 / 4 pixels can be processed parallel in each clock cycle. The FPGA implementation of the proposed architecture uses a Virtex UltraScale XCVU440 device, running at 126 MHz with a throughput of $2 \times 10\wedge 9$ pixels / s, which can be used as a high-performance hardware accelerator for image and video compression encoding.