A Low-Power Two-Step Time-to-Digital Conversion in 28 nm CMOS

In this paper, we propose a two-step time-to-digital converter (TDC) using gated delay technique to reduce power consumption. To reduce power consumption gated delay technology turns the delay chain off when the arbiter is not sampling. Simulation results show that the TDC resolution can reach 7ps when fabricated in 28 nm CMOS process, and the power consumption is reduced by 60% compared to the conventional two-step TDC.