An Encoder Design for High-Speed Pipelined Folding-Interpolation ADC

The paper presents the design of an encoder for high-speed pipelined folding-interpolation (F/I) analog-to-digital converter (ADC). The encoder adopts coarse-fine bit cooperative coding mode, has error-correcting coding function, allows zero-crossing offset, can judge overflow, and is convenient to expand in accuracy. It is suitable for high-speed and high precision pipelined cascaded F/IADC. At the high sampling rate of 1.6GSPS, the single-core ADC in this encoder can achieve an effective resolution of 10.39 bit and an SFDR of 82.6dBc.