A 1.8-V 436-Microwatt 20-kHz Discrete-Time Dynamic Zoom ADC Based on a 2-Stage Floating Inverter Amplifier

This paper proposes a discrete-time (DT) dynamic zoom analog-to-digital converter (ADC). This ADC consists of a coarse 5-bit successive approximation register (SAR) ADC and a fine 1-bit third-order delta-sigma modulator (DSM), which obtains a high resolution efficiently. In this DSM, a highly energy-efficient, robust, and accurate loop filter is implemented by a 2-stage FIA. The ADC is designed and simulated in a 180-nm CMOS process with a sampling frequency (${\mathrm {f}}_{\mathrm{s}}$) of 6-MHz. The simulations show that the dynamic zoom ADC achieves 101.22-dB signal-to-noise-and-distortion ratio (SNDR) at 20-kHz bandwidth (BW), resulting in an SNDR-based Schreier Figure of merit (FoM) of 177.8-dB.