A Delay Matching Technique for Relative Deterministic Jitter Reduction in 28GHz ADPLL

A technique for relative deterministic jitter (DJ) reduction in 28GHz all digital phase-locked loops (ADPLL) is proposed. The reference clock path and feedback clock path of the ADPLL are optimized in 28nm CMOS Technology, especially for CML-to-CMOS circuit, and a delay matching technique is realized to reduce the relative DJ caused by power supply noise between the two input signals of the phase frequency detector (PFD). The frequency of reference clock is 250MHz, while the output clock of ADPLL is 28GHz. The simulation results show that the relative DJ between the two input signals of the PFD is reduced from 1.71ps to 110fs after delay matching.