Design and Implementation of Ultra-Low Power Consumption for High-Performance SoC

In order to reduce the power consumption of a System-on-Chip (SoC) with rich peripherals, this paper proposes a systematic ultra-low power optimization design scheme based on multi-voltage design, power gating and clock gating. First, according to the different application scenarios of the SoC and the enabling requirements of the system cores, memories, interface peripherals and other modules, a variety of power consumption modes are formulated. Then the low power consumption intention of the SoC and the Power Management Unit (PMU) are collaboratively designed, and the control method combining software and hardware is used to realize the efficient transition of SoC power consumption mode. This design scheme uses HHG 110nm process to complete logic synthesis and power analysis. Compared with the original design and normal mode, the power consumption of this design in deep sleep mode is reduced by 89.48% and 62.36% respectively, which greatly reduces the power consumption of the SoC. This paper also demonstrates that in nanoscale circuits, this low-power design scheme has a very high power consumption optimization effect.