A Low Power Dynamic Comparator with Floating Inverter Amplifier for Column-Parallel ADC

This paper presents a low power dynamic comparator for column-parallel Analog-to-Digital Converter (ADC) in CMOS image sensors (CIS). The pre-amplifier in the comparator is based on a floating inverter amplifier, which consists of an inverter-based input pair powered by a floating capacitor, achieves low power consumption. In addition, the preamplifier gain and dynamic power consumption of the comparator is insensitive to the input common-mode voltage. This circuit is implemented in TSMC 40nm CMOS process with a power supply of 0.9V. The simulation results show that the comparator achieves an accuracy of $500\mu \mathrm{V}$ and a power consumption of $2\mu \mathrm{W}$ with 40MHz comparison speed. Furthermore, the layout area is only $5\mu \mathrm{m}\times 35\mu \mathrm{m}$, reducing comparator area while achieving low power consumption.