Two-Step Single-Slope ADC with Three-Stage Bandwidth-Limited Comparator for CMOS Image Sensors

This paper proposes a low-power column parallel two-step single-slope Analog-to-Digital Converter (SS ADC) with three-stage Bandwidth-Limited preamplifier. The slight expanding ramp generator is used to reduce the accuracy error caused by the limited bandwidth. A prototype sensor was designed using UMC 110 nm CMOS image sensors process. The simulation results show that the proposed three-stage Bandwidth-Limited preamplifier consumes $73\mu\mathrm{W}$ power per column, saved 70% power consumption. The DNL is −0.2LSB/ +0.4LSB, INL is −0.2LSB/ +0.3LSB at 20MHz with 3.3V/1.2V supply voltage.