MDCLCG with Square Root Carry Select Adder Technique for Hardware Security

Three-operand adder performs the modular arithmetic operations like addition, multiplication and exponentiation by utilizing various cryptography algorithms. Here, the pseudo-random bit generator algorithm is used to perform addition operation. It performs in binary format and reduces the area, delay, power and increases the speed. In this adder application purpose, the MDCLCG is used to increase the hardware security and light-weighted core. In comparison to all other LCGs and present PBRG techniques, MDCLCG is the more secure and extremely random PRBG approach. The existing MDCLCG can work on the increased operand size but it does not perform well with the three-operand adder to improve the performance. Hence, the SRCSA in integrated to the MDCLCG to obtain better result than existing architectures. Square-Root Carry Save Adder (SRCSA) is one of the simplest techniques used to sequentially add all N partial products by using N-1 adders. This research study intends to improve the implementation of MDCLCG with three-operand binary adder technique for hardware security. The novel MDCLCG architecture can execute 32-bits in Xilinx tool to obtain a better simulation and synthesis result. This architecture is used in addition to the LCGs, FIR and IIR filters, ALU processor, randomness-based verification, etc. These adders execute 8-bits, 16-bits, 32-bits, 64-bits and 128-bits architecture and it is then implemented by using Verilog-HDL and further the synthesis shows the report of less area, less power consumption and high speed with reduced delay than existing architectures.