Design of STT-MRAM Using Hybrid MTJ/CMOS for Applications beyond CMOS

Traditional memory devices are made up of semiconductor materials based on electron charge. But the development of the computing era demands new emerging memories to meet the size and power consumption limitations of SRAM, DRAM, and FLASH, as theexisting memories. Among the upcoming non-volatile memories the Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is capable of becoming the universal memory owing to many advantages like non-volatility, low power consumption, robustness against radiation, high endurance, and compatibility with existing CMOS technologies. In this work, the Verilog-A model is used to realize STT-MRAM. The read and write operations of the basic 1T-1MTJ cell using 45nm CMOS are discussed. The transient analysis, power efficiency, and the current for the STT-MRAM are performed using the Cadence Virtuoso EDA software tool. The work intends to design a non-volatile memory circuit that can be implemented for applications like cache memory, and main memory in the future.