An Optimal Implementation of an 8b/10b Encoder for Xilinx FPGAs

We propose an optimal structural design of an 8b/10b encoder for Xilinx FPGAs. The proposed approach aims at reducing the number of look-up tables used for the implementation. We compare our design with two state-of-the-art solutions and two behavioral models. The implementation results show that our solution provides the lowest resource utilization, logic delay and power consumption.