Design and Analysis of Low Power Full Adder using Reversible Logic

The reversible Logic system will be effective in low power dissipation. For the optimization of power in VLSI design, number of researchers is using reversible logic regularly. In the VLSI design, the use of reversible logic has many advantages because of its high speed, and low power dissipation. This paper provides the design and comparative analysis of reversible full adder using Peres gate with conventional full adder circuits. During comparison it is found that 44% improvement in total thermal power dissipation over the conventional adder circuit. These reversible logic circuits are verified and simulated using Verilog coding, Intel Quartus Prime 20.1