Design of Mesochronous Dual Clock Fifo Buffer with Modified Synchronizer Circuit

In today's substantially scaled technologies, Systems-on-Chip (S oC) suffer from slow wiring as well as process, voltage, temperature (PVT) fluctuations. All these difficulties making synchronous abstractions across larger chips regions more impractical, requiring a significant amount of design work in multiple author approaches to guarantee temporal closure. Because of various phase differences, the transmitter and receiver in this system, which are connected to the mesochronous interface and receive a clock signal, operate at a different frequency. Clock synchronizations are necessary in certain circumstances while sending data across units. The proposed mesochronous FIFO can be developed in a modular manner to support multicycle link delays with less changes to baseline structure. Proposed design consists of only Delay flip-flop and some basic gates to avoid the meta-stability state in FIFO. The delay flip-flop provided sufficient delay to avoid meta-stability state. These synchronizers are need for communication between Tx and Rx side to correctly transfer the data but with some delay. This type of implementation of synchronizers will reduce the hardware complexity of the design compared to the existing method. The proposed method implemented in Xilinx ISE 14.7 version tool and synthesize of the proposed design mesochronous FIFO that use the cadence genus tool with 45nm technology for delay, power and area reports. The proposed design of mesochronous dual clock FIFO buffer with modified synchronizer circuit achieves a power consumption improvement of approximate 10.32% for 64bit mesochronous FIFO.