Complementary Technique of Flight Time Compensation for 6.4 Gbps DDR5 Transmission Link on Dense PCB

In this paper, a complementary technique to compensate and match the flight time or propagation delay of the signals in DDR5 memory bus system on dense printed circuit board (PCB) is proposed. The matched flight time among the traces is achieved with multiple layer transitions using micro vias. This approach complements the conventional serpentine routing in PCB with limited board real estate. The study is carried out with time domain analysis by measuring flight time of the transmission line. The time domain analysis result shows that the flight time is matched within 7.5 ps using multiple micro vias. Furthermore, the frequency response analysis to examine the side effect of this complementary technique indicates that the extra insertion loss contributed by the multiple micro vias is insignificant, i.e., less than 0.25 dB across the full bandwidth of the DDR5 memory operation up to 10 GHz.