Implementation of FOC Algorithm Acceleration Circuit Based on Data Path Calculation

This paper introduces a hardware circuit implementation of a parallel accelerated Field Oriented Control (FOC) algorithm by constructing a data path. It can be generally used in vector control of ultra-high-speed Permanent Magnet Synchronous Motors (PMSM) or Brushless DC Motors (BLDC) to obtain satisfactory bandwidth response. By analyzing the FOC algorithm, the basic data path model of the algorithm is extracted, and the corresponding circuit model is designed based on this. The address scoring and instruction state machine are used to solve the Read-After-Write (RAW) conflict of the data feedback loop. By using the data forwarding method, the operation speed of the PI regulator is optimized as well. The system is implemented with a Single-Instruction-MultipleData (SIMD) pipeline structure. After comprehensive verification, when ARTY-100T experimental board is running at 120MHz clock frequency, only 600ns is needed to complete the calculation of the FOC algorithm.