Design and Implementation of Fine Tuning Phase Shifting Trimmer in III-V Semiconductor Technologies

The need for high-precision digitally-controlled phase shifting blocks that can traverse less than 5
^o
of phase change is quickly arising, especially in domains of complex phased-array systems that are employing double digit of network elements. This paper explores the possibility of implementing such phase shifting blocks on III-V Semiconductor ICs - more specifically in InGaAs and InP - using the phase shifting trimmer architecture. Simulation results (schematic and post-layout extraction) show that it can be done in both InGaAs and InP; where both technology managed to achieve phase steps of less than 0.650o of phase change per bit for an 8-bit phase shifting trimmer. All trimmer phase change responses were linear in InGaAs and InP for all 8-bits of operation. Regular diodes were used in InGaAs; while makeshift HBTs as diode connected transistors were used as the capacitive loadings in the InP trimmer. Both trimmers (InGaAs and InP) were able to traverse small phase changes per bit (sub < 1
o
) with good return loss performance (S11) better than −12dB, and insertion loss (S
21
) of less than 0. 44dB for all bits and phase changes.