A Mixed-Signal Neuron Circuit Implementation using 40nm Technology

This paper presents a mixed-signal neuron circuit implementation for an accelerated LIF array (ALIFA) NIC, designed using the TSMC 40nm PDK technology. The ALIFA operates in the continuous time mixed-signal mode and features largely configurable components with accelerated dynamics. The LIF neurons are interconnected via synapses, and integrate the net current from all the synapses, before emitting an output digital spike. Analogue capacitive memory is implemented to store the circuits’ biasing, which provides wide tuning ranges for synaptic and membrane time constants, as well as refractory periods. The simulation results of the ALIFA convey the same characteristics described by the mathematical model of the LIF. Compared to earlier work, the area consumption has been reduced, as well as power from 14.4μW [1] to 11.5μW. The synapse parameters of the synaptic resistance and time constant ranges are increased to (0.528MΩ-15.873MΩ) and (0.528μs-15.873μs) respectively.