Optimization of Vertical GaN Drift Region Layers for Avalanche and Punch-Through Pn-Diodes

We optimized gallium nitride drift layers for high voltage and low resistance vertical electronic devices by tuning the doping concentration for a given thickness of
$5~\mu \text{m}$
. The optimization procedure is based on an empirical mobility model in order to maximize the corresponding device’s power figure-of-merit with respect to the drift layers parameters. We demonstrate quasi-vertical gallium-nitride based avalanche and punch-through pn-diodes grown on sapphire substrates and we compare the results to the theoretical breakdown voltage values as a function of the drift region doping concentration and thickness. We report on a pn-diode with 545 V avalanche breakdown voltage and a specific resistance of 0.34
$\text{m}\Omega $
cm2 resulting in a power figure-of-merit of 874 MW / cm2 and a punch-through pn-diode with 920 V breakdown voltage, specific resistance of 0.57
$\text{m}\Omega $
cm2 resulting in a power figure-of-merit of 1.48 GW / cm2.