Read Disturbance in Cross-Point Phase-Change Memory Arrays—Part II: Array Simulations Considering External Currents

In Part I of this study, we demonstrated that when a high-read current from phase-change memory (PCM) programmed at a high-SET current (
${I}_{\text {SET}}{)}$
is achieved, melting dynamics in the chalcogenide layer are promoted, thus leading to read disturbances. Therefore, we analyzed additional external current sources that worsened the read disturbances by considering the PCM cell and additional selector and core circuits used in practical applications. By means of HSPICE simulations, the impact of two noticeable external overshoot and inrush currents generated during respective SET and read operations in one-selector and one-PCM (1S-1R) array was investigated. Our findings show that resistance-related components mainly affect the magnitude of the inflowing external current to the 1S-1R cell. The PCM can thus be easily heated up by the current, making the memory state vulnerable to the melting process. For these reasons, we showed that the disturbance primarily observed in the high
${I}_{\text {SET}}$
operated PCM can also occur even at low-
${I}_{\text {SET}}$
settings, given the actual cross-point array environment. Finally, we explored the maximum achievable array size that ensures disturbance-free read endurance by quantifying the read current to examine the location wherein the melting occurs.