Low-Power Dynamic Circuit Design With Steep-Switching Hybrid Phase Transition FETs (Hyper-FETs)

Dynamic logic circuits suffer from leakage current during their evaluation period causing output voltage degradation. Although the keeper transistor is added to protect the output node from leakage, it comes with a considerable area and power penalty. In this article, we propose a novel design topology of a low-power dynamic logic circuit based on steep-switching hybrid phase transition FETs (Hyper-FETs). A Hyper-FET utilizes a phase transition material that exhibits selective insulator-to-metal transition enabling it to overcome the fundamental Boltzmann’s limit. The characteristic feature of the Hyper-FET also includes a higher ON–OFF ratio than the conventional counterpart. We utilize this unique advantage to alleviate the leakage issue in the dynamic circuits. We use a compact model of the phase transition material calibrated with experimental data of a single crystal VO2. For the baseline transistor, we use the predictive technology model of 14-nm FinFET. We comprehensively analyze the effects of different material parameters to explore the scope of further performance improvement. From our analysis, we deduce a range of insulating and metallic state resistance of the phase transition material (PTM) for optimum performance. We also examine the effect of process variation by performing the Monte Carlo variation analysis. Our analysis indicates that the leakage problem of the dynamic circuits is substantially improved as the phase transition material provides an additional high resistance with the pull-down network. We also observe that our design can outperform the conventional dynamic logic circuit even under random process variation.