Dec 2009
1 Hour
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Course content reaffirmed: 06/2015--The access of a memory cell starts when the Word Line is asserted which is controlled by the Word Line Driver and the Row Decoder. This tutorial will focus on the design of the Row Decoder starting with an overview of a basic decoder, and then will describe a greatly improved version that is faster and presents a smaller load to the Address Buffers. The Word Line Driver will be designed such that it is controlled by an internal clock which is critical to the overall timing associated with reading and writing the memory cell. Additional enhancements to the Word Line Driver will be made to reduce the layout area so that it can fit in the small pitch of a memory cell and have increased performance.
IEEE Keywords: CMOS integrated circuits, Circuit synthesis, Circuits and systems, Data models, Data processing, Decoding, Design automation, Integrated circuits, Layout, Memory management, Path planning, Random access memory, SPICE, SRAM chips, Sensors, Signal processing, Tutorials
Persistent Link: https://ieeexplore.ieee.org/servlet/opac?mdnumber=EW1122 More »
Level: Intermediate
Instructor
Doug Sheppard
Doug Sheppard has 33 years experience designing and developing integrated circuits. He is currently President, Owner and founder of Valence, Inc (www.valence-inc.com) that was started in 1993. Valence specializes in digital integrated circuit design with a main focus on memories. Some of the key pro... Show More
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