Kaikai Chi - IEEE Xplore Author Profile
Subscribe
ADVANCED SEARCH

Author details

< Back

Kaikai Chi

Also published under: K. Chi

Publications
93
Citations
1,407
Publications by Year
20062025
Co-Authors:
Show All Co-Authors (145)
Image of author Kaikai Chi

Kaikai Chi

Also published under: K. Chi

Affiliation

School of Computer Science and Technology, Zhejiang University of Technology, China

Publication Topics

Biography

Kaikai Chi (Member, IEEE) received the B.S. and M.S. degrees from Xidian University, Xi’an, China, in 2002 and 2005, respectively, and the Ph.D. degree from Tohoku University, Sendai, Japan, in 2009. He is a Professor with the School of Computer Science and Technology, Zhejiang University of Technology, Hangzhou, China. He has published more than 50 refereed technical papers in proceedings and journals, such as the IEEE Transactions on Wireless Communications, the IEEE Transactions on Vehicular Technology, and the IEEE Transactions on Parallel and Distributed Systems. His current research interests include wireless cellular networks, wireless ad hoc networks, and wireless sensor networks. He was a recipient of the Best Paper Award at the IE...
Publications
93
Citations
1,407
Publications by Year
20062025
Co-Authors:
Show All Co-Authors (145)
Author's Published Works

Showing 1-25 of 188 results

  • Sort

Filter Results

Show

Sort By

Results

NStore: A High-Performance NUMA-Aware Key-Value Store for Hybrid Memory

Zhonghua Wang;Kai Lu;Jiguang Wan;Hong Jiang;Zeyang Zhao;Peng Xu;Biliang Lai;Guokuan Li;Changsheng Xie

IEEE Transactions on Computers
Year: 2025 | Volume: 74, Issue: 3 | Journal Article |
Emerging persistent memory (PM) promises near-DRAM performance, larger capacity, and data persistence, attracting researchers to design PM-based key-value stores. However, existing PM-based key-value stores lack awareness of the Non-Uniform Memory Access (NUMA) architecture on PM, where accessing PM on remote NUMA sockets is considerably slower than accessing local PM. This NUMA-unawareness result...Show More

NStore: A High-Performance NUMA-Aware Key-Value Store for Hybrid Memory

Zhonghua Wang;Kai Lu;Jiguang Wan;Hong Jiang;Zeyang Zhao;Peng Xu;Biliang Lai;Guokuan Li;Changsheng Xie

Year: 2025 | Volume: 74, Issue: 3 | Journal Article |

PeakFS: An Ultra-High Performance Parallel File System via Computing-Network-Storage Co-Optimization for HPC Applications

Yixiao Chen;Haomai Yang;Kai Lu;Wenlve Huang;Jibin Wang;Jiguang Wan;Jian Zhou;Fei Wu;Changsheng Xie

IEEE Transactions on Parallel and Distributed Systems
Year: 2024 | Volume: 35, Issue: 12 | Journal Article |
Emerging high-performance computing (HPC) applications with diverse workload characteristics impose greater demands on parallel file systems (PFSs). PFSs also require more efficient software designs to fully utilize the performance of modern hardware, such as multi-core CPUs, Remote Direct Memory Access (RDMA), and NVMe SSDs. However, existing PFSs expose great limitations under these requirements...Show More

PeakFS: An Ultra-High Performance Parallel File System via Computing-Network-Storage Co-Optimization for HPC Applications

Yixiao Chen;Haomai Yang;Kai Lu;Wenlve Huang;Jibin Wang;Jiguang Wan;Jian Zhou;Fei Wu;Changsheng Xie

Year: 2024 | Volume: 35, Issue: 12 | Journal Article |

Improving DRAM Reliability Using a High Order Error Correction Code

Wei Li;Meng Zhang;Tianwei Gui;Zheng Fang;Changsheng Xie;Fei Wu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2024 | Volume: 43, Issue: 12 | Journal Article |
Dynamic random access memory (DRAM) is being upgraded iteratively, and as a result, its transmission rate and bandwidth are rising quickly. Simultaneously, as the DRAM process has advanced, the storage cell size has decreased and cell integration has improved within each device, leading to a significant boost in storage capacity and density. DRAM has been widely utilized as a crucial storage compo...Show More

Improving DRAM Reliability Using a High Order Error Correction Code

Wei Li;Meng Zhang;Tianwei Gui;Zheng Fang;Changsheng Xie;Fei Wu

Year: 2024 | Volume: 43, Issue: 12 | Journal Article |

PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND Flash

Meng Zhang;Fei Wu;Qin Yu;Changsheng Xie

IEEE Transactions on Device and Materials Reliability
Year: 2024 | Volume: 24, Issue: 1 | Journal Article |
Although three-dimensional (3D) NAND flash memory has demonstrated impressive benefits including high capacity and storage density, data reliability is now a major worry because of long-term storage and ongoing cell wear-out. Low-density parity-check (LDPC) codes are frequently utilized in flash storage systems because of their superior error correcting capabilities to guarantee data reliability. ...Show More

PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND Flash

Meng Zhang;Fei Wu;Qin Yu;Changsheng Xie

Year: 2024 | Volume: 24, Issue: 1 | Journal Article |

FlexZNS: Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones

Yu Wang;You Zhou;Zhonghai Lu;Xiaoyi Zhang;Kun Wang;Feng Zhu;Shu Li;Changsheng Xie;Fei Wu

2023 IEEE 41st International Conference on Computer Design (ICCD)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
NVMe zoned namespace (ZNS) SSDs present a new class of storage devices with attractive features including low cost, software definability, and stable performance. However, one primary culprit that hinders the adoption of ZNS is the high garbage collection (GC) overhead it brings to host software. The ZNS interface divides the logical address space into size-fixed zones that must be written sequent...Show More

FlexZNS: Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones

Yu Wang;You Zhou;Zhonghai Lu;Xiaoyi Zhang;Kun Wang;Feng Zhu;Shu Li;Changsheng Xie;Fei Wu

Year: 2023 | Conference Paper |

ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER Variation

Meng Zhang;Xiaoyi Zhang;Fei Wu;Kai Tao;Feng Zhu;Shu Li;Yahui Zhao;Changsheng Xie

IEEE Transactions on Consumer Electronics
Year: 2023 | Volume: 69, Issue: 4 | Journal Article |
Cited by: Papers (4)
Three-dimensional (3D) NAND flash memory has been frequently utilized in consumer electronics as a popular storage device. However, data reliability has become an important problem to be solved. Low-density parity-check (LDPC) codes with superior error correction capability are commonly used in 3D NAND flash memory to ensure data reliability. Unfortunately, high raw bit error rate (RBER) induced b...Show More

ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER Variation

Meng Zhang;Xiaoyi Zhang;Fei Wu;Kai Tao;Feng Zhu;Shu Li;Yahui Zhao;Changsheng Xie

Year: 2023 | Volume: 69, Issue: 4 | Journal Article |

Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs

Yu Wang;You Zhou;Fei Wu;Yu Zhong;Jian Zhou;Zhonghai Lu;Shu Li;Zhengyong Wang;Changsheng Xie

IEEE Transactions on Computers
Year: 2023 | Volume: 72, Issue: 11 | Journal Article |
Cited by: Papers (1)
Background (BG) tasks are maintained indispensably in multiple layers of storage systems, from applications to flash-based SSDs. They launch a large amount of I/Os, causing significant interference with foreground (FG) I/O performance. Our key insight is that, to mitigate such interference, holistic scheduling of system-wide, multi-source BG I/Os is required and can only be realized at the underly...Show More

Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs

Yu Wang;You Zhou;Fei Wu;Yu Zhong;Jian Zhou;Zhonghai Lu;Shu Li;Zhengyong Wang;Changsheng Xie

Year: 2023 | Volume: 72, Issue: 11 | Journal Article |

Pipette: Efficient Fine-Grained Reads for SSDs

Shuhan Bai;Hu Wan;Yun Huang;Xuan Sun;Fei Wu;Changsheng Xie;Hung-Chih Hsieh;Tei-Wei Kuo;Chun Jason Xue

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2023 | Volume: 42, Issue: 12 | Journal Article |
Big data applications, such as recommendation system and social network, often generate a huge number of fine-grained reads to the storage. Block-oriented storage devices upon the traditional storage system rely on the paging mechanism to migrate pages to the host DRAM, tending to suffer from these fine-grained read operations in terms of I/O traffic as well as performance. Motivated by this chall...Show More

Pipette: Efficient Fine-Grained Reads for SSDs

Shuhan Bai;Hu Wan;Yun Huang;Xuan Sun;Fei Wu;Changsheng Xie;Hung-Chih Hsieh;Tei-Wei Kuo;Chun Jason Xue

Year: 2023 | Volume: 42, Issue: 12 | Journal Article |

eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory

Meng Zhang;Fei Wu;Qin Yu;Neidong Fu;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2023 | Volume: 42, Issue: 6 | Journal Article |
Cited by: Papers (2)
Low read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error ...Show More

eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory

Meng Zhang;Fei Wu;Qin Yu;Neidong Fu;Changsheng Xie

Year: 2023 | Volume: 42, Issue: 6 | Journal Article |

PACA: A Page Type Aware Read Cache Scheme in QLC Flash-based SSDs

Qihui Chen;Shuai Wang;You Zhou;Fei Wu;Shu Li;Zhengyong Wang;Changsheng Xie

2022 IEEE 40th International Conference on Computer Design (ICCD)
Year: 2022 | Conference Paper |
Cited by: Papers (4)
QLC flash-based SSDs are gaining increasing attention and are expected to be widely used in read-intensive application scenarios, since they provide high density and low cost but suffer from poor write endurance and performance. QLC flash has four types of pages, between which read latency variation is as large as 1.6 to 4.8 times. This raises a critical concern for QLC SSDs to provide adequate an...Show More

PACA: A Page Type Aware Read Cache Scheme in QLC Flash-based SSDs

Qihui Chen;Shuai Wang;You Zhou;Fei Wu;Shu Li;Zhengyong Wang;Changsheng Xie

Year: 2022 | Conference Paper |

WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs

Yuhong Wen;You Zhou;Fei Wu;Shu Li;Zhenghong Wang;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 11 | Journal Article |
Cited by: Papers (2)
Sharing a flash-based solid-state drive (SSD) among multiple tenants has become a common practice to improve storage utilization and cost efficiency. Meanwhile, how to allocate limited storage resources, especially the over-provisioning space (OPS) resources, among competitive tenants has emerged as a critical problem. The OPS refers to additional user-invisible storage space, whose size influence...Show More

WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs

Yuhong Wen;You Zhou;Fei Wu;Shu Li;Zhenghong Wang;Changsheng Xie

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

Error Generation for 3D NAND Flash Memory

Weihua Liu;Fei Wu;Songmiao Meng;Xiang Chen;Changsheng Xie

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2022 | Conference Paper |
Cited by: Papers (6)
Three-dimension (3D) NAND flash memory is the preferred storage component of solid-state drive (SSD) for its high ratio of capacity and cost. Optimizing the reliability of modern SSD needs to test and collect a large amount of real-world error data from 3D NAND flash memory. However, the test costs have surged dozens of times as its capacity increases. It's imperative to reduce the costs of testin...Show More

Error Generation for 3D NAND Flash Memory

Weihua Liu;Fei Wu;Songmiao Meng;Xiang Chen;Changsheng Xie

Year: 2022 | Conference Paper |

FenceKV: Enabling Efficient Range Query for Key-Value Separation

Chenlei Tang;Jiguang Wan;Changsheng Xie

IEEE Transactions on Parallel and Distributed Systems
Year: 2022 | Volume: 33, Issue: 12 | Journal Article |
Cited by: Papers (16)
LSM-tree is widely used in key-value stores for big data storage, but it suffers from write amplification brought by frequent compaction operations. An effective solution for this problem is key-value separation, which decouples values from the LSM-tree and stores them in a separate value log. However, existing key-value separation schemes achieve poor range query performance, especially for small...Show More

FenceKV: Enabling Efficient Range Query for Key-Value Separation

Chenlei Tang;Jiguang Wan;Changsheng Xie

Year: 2022 | Volume: 33, Issue: 12 | Journal Article |

Understanding and Exploiting the Full Potential of SSD Address Remapping

Qiulin Wu;You Zhou;Fei Wu;Hong Jiang;Jian Zhou;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 11 | Journal Article |
Cited by: Papers (5)
Duplicate writes are prevalent in storage systems, originating from data duplication, journaling, and data relocations, etc. As flash-based solid state drives (SSDs) have been widely deployed, duplicate writes can significantly degrade their performance and lifetime. Prior studies have proposed innovative approaches that exploit the address remapping utility inside an SSD to eliminate duplicate wr...Show More

Understanding and Exploiting the Full Potential of SSD Address Remapping

Qiulin Wu;You Zhou;Fei Wu;Hong Jiang;Jian Zhou;Changsheng Xie

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory

Bin Zhou;Ting Ye;Shenggang Wan;Xubin He;Weijun Xiao;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 11 | Journal Article |
Cited by: Papers (1)
Multilevel cell (MLC) NAND flash memory uses the voltages of the memory cells to represent bits, but high voltages cause much more damage on the cells than low voltages. Free space in MLC can be leveraged to reduce the usage of the high voltages and thus extend the lifetime of MLC. However, limited by the conventional data representation rule that represents bits by the voltage of one single cell,...Show More

Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory

Bin Zhou;Ting Ye;Shenggang Wan;Xubin He;Weijun Xiao;Changsheng Xie

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

Lanlan Cui;Xiaojian Liu;Fei Wu;Zhonghai Lu;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 6 | Journal Article |
Cited by: Papers (3)
For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-...Show More

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

Lanlan Cui;Xiaojian Liu;Fei Wu;Zhonghai Lu;Changsheng Xie

Year: 2022 | Volume: 41, Issue: 6 | Journal Article |

A-Cache: Asymmetric Buffer Cache for RAID-10 Systems Under a Single-Disk Failure to Significantly Boost Availability

Bin Zhou;Hong Jiang;Qiang Cao;Shenggang Wan;Changsheng Xie

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 3 | Journal Article |
Cited by: Papers (2)
The RAID-10 architecture has been widely deployed in commercial and industrial storage environments over the past two decades due to its high reliability, availability, and performance. However, during the recovery process of a single disk failure, which accounts for more than 99.75% of the disk failure scenarios, it is still at a high risk of data loss and suffers from a degradation of user I/O p...Show More

A-Cache: Asymmetric Buffer Cache for RAID-10 Systems Under a Single-Disk Failure to Significantly Boost Availability

Bin Zhou;Hong Jiang;Qiang Cao;Shenggang Wan;Changsheng Xie

Year: 2022 | Volume: 41, Issue: 3 | Journal Article |

Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write Amplification

You Zhou;Ke Wang;Fei Wu;Changsheng Xie;Hao Lv

2021 IEEE 39th International Conference on Computer Design (ICCD)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
Log-structured file systems (LS-FSs) sequentialize writes, so they are expected to perform well on flash-based SSDs. However, we observe a semantic gap between the LS- FS and SSD that causes a stale-LBA problem. When data are updated, the LS-FS allocates new logical block addresses (LBAs). The relevant stale LBAs are invalidated and then trimmed or reused with a delay by the LS-FS. During the time...Show More

Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write Amplification

You Zhou;Ke Wang;Fei Wu;Changsheng Xie;Hao Lv

Year: 2021 | Conference Paper |

Intelligent Prediction of Flash Lifetime via Online Domain Adaptation

Ruixiang Ma;Fei Wu;Changsheng Xie

2021 IEEE 39th International Conference on Computer Design (ICCD)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
To resolve the low generalization ability of the flash lifetime model caused by a small training sample, we propose a multiple source ensemble online domain adaptation scheme, called MSE. MSE uses multiple offline source blocks to assist in establishing a lifetime prediction model for the online target block. MSE migrates information from these blocks to the target block, effectively solving the p...Show More

Intelligent Prediction of Flash Lifetime via Online Domain Adaptation

Ruixiang Ma;Fei Wu;Changsheng Xie

Year: 2021 | Conference Paper |

EFLOG: A Full Stream-Logging Scheme with Erasure Coding in Cloud Storage Systems

Lei Sun;Qiang Cao;Shucheng Wang;Changsheng Xie

2021 IEEE International Conference on Networking, Architecture and Storage (NAS)
Year: 2021 | Conference Paper |
Large-scale cloud storage systems use the logging mechanism to sequentially write data in an append-only manner. The write stream needs to be first appended and persisted into logging files, and then encoded with erasure coding (EC) in underlying storage. This introduces significant overhead to small write operations. To solve this problem, we propose EFLOG, a full-streaming storage framework that...Show More

EFLOG: A Full Stream-Logging Scheme with Erasure Coding in Cloud Storage Systems

Lei Sun;Qiang Cao;Shucheng Wang;Changsheng Xie

Year: 2021 | Conference Paper |

Building A Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage

Peng Xu;Nannan Zhao;Jiguang Wan;Wei Liu;Shuning Chen;Yuanhui Zhou;Hadeel Albahar;Hanyang Liu;Liu Tang;Changsheng Xie

2021 IEEE International Conference on Cluster Computing (CLUSTER)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
The explosive growth of modern web-scale applications has made cost-effectiveness a primary design goal for their underlying databases. As a backbone of modern databases, LSM-tree based key-value stores (LSM store) face limited storage options. They are either designed for local storage that is relatively small, expensive, and fast or for cloud storage that offers larger capacities at reduced cost...Show More

Building A Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage

Peng Xu;Nannan Zhao;Jiguang Wan;Wei Liu;Shuning Chen;Yuanhui Zhou;Hadeel Albahar;Hanyang Liu;Liu Tang;Changsheng Xie

Year: 2021 | Conference Paper |

VRefine: Refining Massive Surveillance Videos for Efficient Store and Fast Analyzing

Chen Zhang;Qiang Cao;Jie Yao;Changsheng Xie

2021 IEEE/ACM 21st International Symposium on Cluster, Cloud and Internet Computing (CCGrid)
Year: 2021 | Conference Paper |
Ubiquitous cameras continuously produce enormous surveillance videos, largely challenging the capacity of video analytics and storage system. Although such videos are encoded and compressed by codecs to effectively reduce inter-/intra-frame redundancy at pixel level, they still consume massive storage space, thus being deleted periodically to recycle storage. To reduce hardware pressure in both ef...Show More

VRefine: Refining Massive Surveillance Videos for Efficient Store and Fast Analyzing

Chen Zhang;Qiang Cao;Jie Yao;Changsheng Xie

Year: 2021 | Conference Paper |

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory

Weihua Liu;Fei Wu;Jian Zhou;Meng Zhang;Chengmo Yang;Zhonghai Lu;Yu Wang;Changsheng Xie

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2021 | Conference Paper |
Cited by: Papers (14)
3D NAND flash memory faces unprecedented complicated interference than planar NAND flash memory, resulting in more concern regarding reliability and performance. Stronger error correction code (ECC) and adaptive reading strategies are proposed to improve the reliability and performance taking a threshold voltage (Vth) distribution model as the backbone. However, the existing modeling methods are c...Show More

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory

Weihua Liu;Fei Wu;Jian Zhou;Meng Zhang;Chengmo Yang;Zhonghai Lu;Yu Wang;Changsheng Xie

Year: 2021 | Conference Paper |

SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging

Qiulin Wu;You Zhou;Fei Wu;Ke Wang;Hao Lv;Jiguang Wan;Changsheng Xie

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
Write-ahead logging (WAL) has been widely used to provide transactional atomicity in databases, such as SQLite and MySQL/InnoDB. However, the WAL introduces duplicate writes, where changes are recorded in the WAL file and then written to the database file, called checkpointing writes. On the other hand, NAND flash-based SSDs, which have an inherent indirection software layer, called flash translat...Show More

SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging

Qiulin Wu;You Zhou;Fei Wu;Ke Wang;Hao Lv;Jiguang Wan;Changsheng Xie

Year: 2021 | Conference Paper |

Exploiting Resistance Drift Characteristics to Improve Reliability of LDPC-Assisted Phase-Change Memory

Meng Zhang;Fei Wu;Qin Yu;Weihua Liu;Ruixiang Ma;Changsheng Xie

IEEE Transactions on Device and Materials Reliability
Year: 2021 | Volume: 21, Issue: 3 | Journal Article |
Cited by: Papers (2)
Phase-change memory (PCM) as emerging non-volatile memory has attracted more attention and considered as the promising replacement of the main memory. PCM has shown good scalability and high storage density, but data storage reliability has become a challenge and concern. When data are written into PCM cells by a phase transition between amorphous and crystalline, the resistance of each state drif...Show More

Exploiting Resistance Drift Characteristics to Improve Reliability of LDPC-Assisted Phase-Change Memory

Meng Zhang;Fei Wu;Qin Yu;Weihua Liu;Ruixiang Ma;Changsheng Xie

Year: 2021 | Volume: 21, Issue: 3 | Journal Article |

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.