Willem Perold - IEEE Xplore Author Profile
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Willem Perold

Also published under: W. J. Perold, Willem Jacobus Perold, W. Perold, Willem Jakobus Perold, Willem J. Perold

Publications
38
Citations
174
Publications by Year
19882020
Co-Authors:
Show All Co-Authors (30)
Image of author Willem Perold

Willem Perold

Also published under: W. J. Perold, Willem Jacobus Perold, W. Perold, Willem Jakobus Perold, Willem J. Perold

Affiliation

Department of Electrical and Electronic Engineering
Stellenbosch University
Stellenbosch, South Africa

Publication Topics

Biography

Willem Perold (Senior Member, IEEE) received the master’s, Ph.D., and D.Eng. degrees in electronic engineering from the University of Stellenbosch in 1977, 1986, and 2017, respectively. He has been appointed as a Lecturer and a Researcher with the Department of Electrical and Electronic Engineering, Stellenbosch University, since 1982, where he is currently a Full Professor and also the Vice Dean of Research with the Faculty of Engineering. His research interests include solid state physics, electronic circuit simulation, superconducting circuits and devices, and nanosensors.(Based on document published on 3 February 2020).
Publications
38
Citations
174
Publications by Year
19882020
Co-Authors:
Show All Co-Authors (30)
Author's Published Works

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Innovation in solid state devices for exascale computing

Tze-chiang Chen

Proceedings of 2010 International Symposium on VLSI Technology, System and Application
Year: 2010 | Conference Paper |
Cited by: Papers (2)
The continuous scaling of CMOS technology has enabled system performance to double every two years for the past 40 years. However, new classes of applications will demand a much faster rate of improvement such as 2×/year in order to reach exaflop capabilities by the end of this decade. These applications represent a significant growth opportunity and require continued innovation in solid state tec...Show More

Innovation in solid state devices for exascale computing

Tze-chiang Chen

Year: 2010 | Conference Paper |

Challenges for silicon technology scaling in the nanoscale era

Tze-chiang Chen

2009 Proceedings of the European Solid State Device Research Conference
Year: 2009 | Conference Paper |
Cited by: Papers (1)
The continuous and systematic increase in transistor density and performance, as described in ldquoMoore's Lawrdquo and guided by CMOS scaling theory, has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variabil...Show More

Challenges for silicon technology scaling in the nanoscale era

Tze-chiang Chen

Year: 2009 | Conference Paper |

Challenges for silicon technology scaling in the Nanoscale Era

Tze-chiang Chen

2009 Proceedings of ESSCIRC
Year: 2009 | Conference Paper |
Cited by: Papers (9) | Patents (1)
The continuous and systematic increase in transistor density and performance, as described in ldquoMoore's Lawrdquo and guided by CMOS scaling theory, has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variabil...Show More

Challenges for silicon technology scaling in the Nanoscale Era

Tze-chiang Chen

Year: 2009 | Conference Paper |

Device technology innovation for exascale computing

Tze-chiang Chen

2009 Symposium on VLSI Technology
Year: 2009 | Conference Paper |
Cited by: Papers (8)
For the past 40 years, the scaling of CMOS device technology has enabled system performance to double every two years. However, emerging classes of applications for which network-speed processing and data-intensive modeling are integral components will demand a much faster rate of improvement, such as 2x/year in order to reach exaflop capabilities (100x–1000x over present systems) by the end of th...Show More

Device technology innovation for exascale computing

Tze-chiang Chen

Year: 2009 | Conference Paper |

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik;B. Doris;R. Mo;J. Sleight;E. Cartier;C. Dewan;D. Park;H. Bu;W. Natzle;W. Yan;C. Ouyang;K. Henson;D. Boyd;S. Callegari;R. Carter;D. Casarotto;M. Gribelyuk;M. Hargrove;W. He;Y. Kim;B. Linder;N. Moumen;V. K. Paruchuri;J. Stathis;M. Steen;A. Vayshenker;X. Wang;S. Zafar;T. Ando;R. Iijima;M. Takayanagi;V. Narayanan;R. Wise;Y. Zhang;R. Divakaruni;M. Khare;T. C. Chen

2007 IEEE Symposium on VLSI Technology
Year: 2007 | Conference Paper |
Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å...Show More

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik;B. Doris;R. Mo;J. Sleight;E. Cartier;C. Dewan;D. Park;H. Bu;W. Natzle;W. Yan;C. Ouyang;K. Henson;D. Boyd;S. Callegari;R. Carter;D. Casarotto;M. Gribelyuk;M. Hargrove;W. He;Y. Kim;B. Linder;N. Moumen;V. K. Paruchuri;J. Stathis;M. Steen;A. Vayshenker;X. Wang;S. Zafar;T. Ando;R. Iijima;M. Takayanagi;V. Narayanan;R. Wise;Y. Zhang;R. Divakaruni;M. Khare;T. C. Chen

Year: 2007 | Conference Paper |

Band Edge High-κ/Metal Gate n-MOSFETs Using Ultra Thin Capping Layers

V. K. Paruchuri;V. Narayanan;B. P. Linder;S.L. Brown;Y. H. Kim;Y. Wang;P. Ronsheim;R. Jammy;T. C. Chen

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Year: 2007 | Conference Paper |
Cited by: Papers (4)
Ultra thin layers of Magnesium containing cap layers are deposited on Hf based dielectrics prior to deposition of the TiN/Poly-Si electrode stack [1] to achieve Band-edge (BE) high-κ/metal nMOSFETs with good mobility (190 cm2/Vs @ 1 MV/cm) at Tinv (1.45 nm), in a gate first process flow. It is shown that Vt can be modulated anywhere between midgap and band edge by changing the cap layer thickness....Show More

Band Edge High-κ/Metal Gate n-MOSFETs Using Ultra Thin Capping Layers

V. K. Paruchuri;V. Narayanan;B. P. Linder;S.L. Brown;Y. H. Kim;Y. Wang;P. Ronsheim;R. Jammy;T. C. Chen

Year: 2007 | Conference Paper |

Characterization of the Ultrathin $\hbox{HfO}_{2}$ and Hf-Silicate Films Grown by Atomic Layer Deposition

Tze Chiang Chen;Cheng-Yi Peng;Chih-Hung Tseng;Ming-Han Liao;Mei-Hsin Chen;Chih-I Wu;Ming-Yau Chern;Pei-Jer Tzeng;Chee Wee Liu

IEEE Transactions on Electron Devices
Year: 2007 | Volume: 54, Issue: 4 | Journal Article |
Cited by: Papers (34)
The physical properties of $\hbox{HfO}_{2}$ and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 $\hbox{cm}^{-1}$ originate from Hf–O–Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the...Show More

Characterization of the Ultrathin $\hbox{HfO}_{2}$ and Hf-Silicate Films Grown by Atomic Layer Deposition

Tze Chiang Chen;Cheng-Yi Peng;Chih-Hung Tseng;Ming-Han Liao;Mei-Hsin Chen;Chih-I Wu;Ming-Yau Chern;Pei-Jer Tzeng;Chee Wee Liu

Year: 2007 | Volume: 54, Issue: 4 | Journal Article |

Where CMOS is Going: Trendy Hype vs. Real Technology

Tze-Chiang Chen

IEEE Solid-State Circuits Society Newsletter
Year: 2006 | Volume: 11, Issue: 3 | Journal Article |
Cited by: Papers (37)
Two important challenges facing Moore's Law and continued CMOS scaling are growing standby power dissipation and the increasing variability in device characteristics. Cooperative circuit/technology co-design and architectures developed in conjunction with new materials and device structures will provide a comprehensive solution to these challenges Show More

Where CMOS is Going: Trendy Hype vs. Real Technology

Tze-Chiang Chen

Year: 2006 | Volume: 11, Issue: 3 | Journal Article |

Overcoming research challenges for CMOS scaling: industry directions

Tze-chiang Chen

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
Year: 2006 | Conference Paper |
Cited by: Papers (49)
The development of silicon technology has been, and will continue to be, driven by system needs. The continuous and systematic increase in transistor density and performance, guided by CMOS scaling theory (Dennard et al., 1974) and described in "Moore's Law" (Moore, 1975), has been a highly successful process for the development of silicon technology for the past 40 years. As the silicon industry ...Show More

Overcoming research challenges for CMOS scaling: industry directions

Tze-chiang Chen

Year: 2006 | Conference Paper |

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

T.C. Chen;G. Shahidi;S. Guha;M. Ieong;M.P. Chudzik;R. Jammy;P. Ronsheim;P.E. Batson;Y. Wang;D.L. Lacey;J.-P. Locquet;P. Jamison;A. Callegari;E. Cartier;M. Steen;M. Copel;J. Arnold;S. Brown;J. Stathis;S. Zafar;Y.H. Kim;B. Doris;B.P. Linder;N.A. Bojarczuk;V.K. Paruchuri;V. Narayanan

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.
Year: 2006 | Conference Paper |
We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack,...Show More

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

T.C. Chen;G. Shahidi;S. Guha;M. Ieong;M.P. Chudzik;R. Jammy;P. Ronsheim;P.E. Batson;Y. Wang;D.L. Lacey;J.-P. Locquet;P. Jamison;A. Callegari;E. Cartier;M. Steen;M. Copel;J. Arnold;S. Brown;J. Stathis;S. Zafar;Y.H. Kim;B. Doris;B.P. Linder;N.A. Bojarczuk;V.K. Paruchuri;V. Narayanan

Year: 2006 | Conference Paper |

Thickness measurement of ultra-thin gate dielectrics under inversion condition

W.J. Zhu;M. Khare;J. Snare;P.R. Varekamp;S.H. Ku;P. Agnello;T.C. Chen;T.P. Ma

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)
Year: 2001 | Conference Paper |
Cited by: Papers (2)
Accurate measurement of inversion thickness is essential in ULSI technology for development and control of ultra-thin gate dielectric processes. However, the accuracy of the measurement can be severely affected by the high gate leakage current and series resistance. This paper presents a methodology to reduce the measurement error by optimizing the ac modulation frequency and test device structure...Show More

Thickness measurement of ultra-thin gate dielectrics under inversion condition

W.J. Zhu;M. Khare;J. Snare;P.R. Varekamp;S.H. Ku;P. Agnello;T.C. Chen;T.P. Ma

Year: 2001 | Conference Paper |

Partially depleted silicon-on-insulator (SOI): a device design/modeling and circuit perspective

F. Assaderaghi;G. Shahidi;S. Fung;M. Sherony;L. Wagner;J. Sleight;S.H. Lo;K. Wu;T.-C. Chen

ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453)
Year: 2000 | Conference Paper |
Cited by: Papers (1) | Patents (1)
This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategi...Show More

Partially depleted silicon-on-insulator (SOI): a device design/modeling and circuit perspective

F. Assaderaghi;G. Shahidi;S. Fung;M. Sherony;L. Wagner;J. Sleight;S.H. Lo;K. Wu;T.-C. Chen

Year: 2000 | Conference Paper |

Design of a high performance PD SOI for the 0.18 /spl mu/m technology generation

M.J. Sherony;S.-H. Lo;R. Schulz;E. Leobandung;N. Zamdmer;J.W. Sleight;W. Rausch;F. Assaderaghi;T.C. Chen;G.G. Shahidi

ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453)
Year: 2000 | Conference Paper |
This paper presents an optimized partially-depleted SOI device design for the 0.18 /spl mu/m CMOS technology generation and addresses several SOI unique floating-body effect issues which can affect the design. It is demonstrated that through proper device optimization, these undesired SOI-specific issues can be minimized to improve the manufacturability while maintaining high performance. Inverter...Show More

Design of a high performance PD SOI for the 0.18 /spl mu/m technology generation

M.J. Sherony;S.-H. Lo;R. Schulz;E. Leobandung;N. Zamdmer;J.W. Sleight;W. Rausch;F. Assaderaghi;T.C. Chen;G.G. Shahidi

Year: 2000 | Conference Paper |

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

S.K.H. Fung;N. Zamdmer;P.J. Oldiges;J. Sleight;A. Mocuta;M. Sherony;S.-H. Lo;R. Joshi;C.T. Chuang;I. Yang;S. Crowder;T.C. Chen;F. Assaderaghi;G. Shahidi

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
Year: 2000 | Conference Paper |
The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that ...Show More

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

S.K.H. Fung;N. Zamdmer;P.J. Oldiges;J. Sleight;A. Mocuta;M. Sherony;S.-H. Lo;R. Joshi;C.T. Chuang;I. Yang;S. Crowder;T.C. Chen;F. Assaderaghi;G. Shahidi

Year: 2000 | Conference Paper |

Anomalous low temperature charge leakage mechanism in ULSI flash memories

C. Lam;T. Sunaga;Y. Igarashi;M. Ichinose;K. Kitamura;C. Willets;J. Johnson;S. Mittl;F. White;H. Tang;T.-C. Chen

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
Year: 2000 | Conference Paper |
Cited by: Papers (5)
We present a systematic study of an anomalous charge leakage phenomenon in flash memories which occurs at temperatures below 150/spl deg/C. Essential characteristics of the leakage are described in association with various process parameters. A new leakage mechanism based on diffusion of an ionic entity produced by regenerative electrochemical reactions through percolating networks in the silicon ...Show More

Anomalous low temperature charge leakage mechanism in ULSI flash memories

C. Lam;T. Sunaga;Y. Igarashi;M. Ichinose;K. Kitamura;C. Willets;J. Johnson;S. Mittl;F. White;H. Tang;T.-C. Chen

Year: 2000 | Conference Paper |

Impact of the gate-to-body tunneling current on SOI history effect

S.K.H. Fung;N. Zamdmer;I. Yang;M. Sherony;Shih-Hsieh Lo;L. Wagner;T.-C. Chen;G. Shahidi;F. Assaderaghi

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)
Year: 2000 | Conference Paper |
Cited by: Papers (13)
The gate dielectric thickness has been aggressively scaled in recent technology generations. The thin gate dielectric is essential to maintain and improve the performance at reduced supply voltages and to control the short-channel effect. For very thin dielectrics, the gate tunneling current becomes noticeable. A component of this tunneling current is comprised of the body majority carriers tunnel...Show More

Impact of the gate-to-body tunneling current on SOI history effect

S.K.H. Fung;N. Zamdmer;I. Yang;M. Sherony;Shih-Hsieh Lo;L. Wagner;T.-C. Chen;G. Shahidi;F. Assaderaghi

Year: 2000 | Conference Paper |

A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

P. Smeys;V. McGahay;I. Yang;J. Adkisson;K. Beyer;O. Bula;Z. Chen;B. Chu;J. Culp;S. Das;A. Eckert;L. Hadel;M. Hargrove;J. Herman;L. Lin;R. Mann;E. Maciejewski;S. Narasimha;P. O'Neil;S. Rauch;D. Ryan;J. Toomey;L. Tsou;P. Varekamp;R. Wachnik;T. Wagner;S. Wu;C. Yu;P. Agnello;J. Connolly;S. Crowder;C. Davis;R. Ferguson;A. Sekiguchi;L. Su;R. Goldblatt;T.C. Chen

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
Year: 2000 | Conference Paper |
Cited by: Papers (14)
This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect per...Show More

A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

P. Smeys;V. McGahay;I. Yang;J. Adkisson;K. Beyer;O. Bula;Z. Chen;B. Chu;J. Culp;S. Das;A. Eckert;L. Hadel;M. Hargrove;J. Herman;L. Lin;R. Mann;E. Maciejewski;S. Narasimha;P. O'Neil;S. Rauch;D. Ryan;J. Toomey;L. Tsou;P. Varekamp;R. Wachnik;T. Wagner;S. Wu;C. Yu;P. Agnello;J. Connolly;S. Crowder;C. Davis;R. Ferguson;A. Sekiguchi;L. Su;R. Goldblatt;T.C. Chen

Year: 2000 | Conference Paper |

A partially-depleted SOI compact model - formulation and parameter extraction

S.K.H. Fung;L. Wagner;M. Sherony;N. Zamdmer;J. Sleight;M. Michel;E. Leobandung;S.H. Lo;T.C. Chen;F. Assaderaghi

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
Year: 2000 | Conference Paper |
Cited by: Papers (4)
As SOI technology advances into mainstream, an accurate and predictive compact model is necessary to ensure the success of VLSI chip design. This paper describes a compact model which contributes to the successful implementation of the sophisticated 660 MHz 64-bit PowerPC at its first design. This model captures all important SOI specific device characteristics and circuit behavior properly. The p...Show More

A partially-depleted SOI compact model - formulation and parameter extraction

S.K.H. Fung;L. Wagner;M. Sherony;N. Zamdmer;J. Sleight;M. Michel;E. Leobandung;S.H. Lo;T.C. Chen;F. Assaderaghi

Year: 2000 | Conference Paper |

Array pass transistor design in trench cell for Gbit DRAM and beyond

Y. Li;J. Mandelman;P. Parries;Y. Matsubara;Q. Ye;R. Rengarajan;J. Alsmeier;B. Flietner;D. Wheeler;H. Akatsu;R. Divakaruni;R. Mohler;K. Sunouchi;G. Bronner;T.C. Chen

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)
Year: 1999 | Conference Paper |
Cited by: Papers (5) | Patents (2)
Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engine...Show More

Array pass transistor design in trench cell for Gbit DRAM and beyond

Y. Li;J. Mandelman;P. Parries;Y. Matsubara;Q. Ye;R. Rengarajan;J. Alsmeier;B. Flietner;D. Wheeler;H. Akatsu;R. Divakaruni;R. Mohler;K. Sunouchi;G. Bronner;T.C. Chen

Year: 1999 | Conference Paper |

High performance 0.18 /spl mu/m SOI CMOS technology

E. Leobandung;E. Barth;M. Sherony;S.-H. Lo;R. Schulz;W. Chu;M. Khare;D. Sadana;D. Schepis;R. Boiam;I. Sleight;F. White;F. Assaderaghi;D. Moy;G. Biery;R. Goldblan;T.-C. Chen;B. Davari;G. Shahidi

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
Year: 1999 | Conference Paper |
Cited by: Papers (8)
A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half pitch generation) and devices than previously reported 0.18 /spl mu/m CMOS technology, low dose SIMOX SOI substrate, dual gate oxide, low /spl epsi/ BEOL insulator, and 7 layer copper metalization. Inverter delay of less than 6.5 ps has been ac...Show More

High performance 0.18 /spl mu/m SOI CMOS technology

E. Leobandung;E. Barth;M. Sherony;S.-H. Lo;R. Schulz;W. Chu;M. Khare;D. Sadana;D. Schepis;R. Boiam;I. Sleight;F. White;F. Assaderaghi;D. Moy;G. Biery;R. Goldblan;T.-C. Chen;B. Davari;G. Shahidi

Year: 1999 | Conference Paper |

Mainstreaming of the SOI technology

G. Shahidi;A. Ajmera;F. Assaderaghi;R. Bolam;A. Bryant;M. Coffey;H. Hovel;J. Lasky;E. Leobandung;H.-S. Lo;M. Maloney;D. Moy;W. Rausch;D. Sadana;D. Schepis;M. Sherony;J.W. Sleight;L.F. Wagner;K. Wu;B. Davari;T.C. Chen

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)
Year: 1999 | Conference Paper |
Cited by: Papers (24)
Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.Show More

Mainstreaming of the SOI technology

G. Shahidi;A. Ajmera;F. Assaderaghi;R. Bolam;A. Bryant;M. Coffey;H. Hovel;J. Lasky;E. Leobandung;H.-S. Lo;M. Maloney;D. Moy;W. Rausch;D. Sadana;D. Schepis;M. Sherony;J.W. Sleight;L.F. Wagner;K. Wu;B. Davari;T.C. Chen

Year: 1999 | Conference Paper |

Characteristics of vertical p-channel MOSFETs for high density circuit application

D.S. Wen;W.H. Chang;T.V. Rajeevakumar;G.B. Bronner;P.A. McFarland;Y. Lii;T.C. Chen;F.L. Pesavento;M.P. Manny;W. Hwang;S.H. Dhong

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers
Year: 1991 | Conference Paper |
Vertical p-channel MOSFETs have been experimentally fabricated and characterized. Device characteristics of vertical p-channel MOSFETs are comparable to those of planar surface devices. Conduction current of a vertical transistor can be increased as much as four times that of a planar transistor for the same device area. The feature of large W/L ratio allows further increase in device density. Con...Show More

Characteristics of vertical p-channel MOSFETs for high density circuit application

D.S. Wen;W.H. Chang;T.V. Rajeevakumar;G.B. Bronner;P.A. McFarland;Y. Lii;T.C. Chen;F.L. Pesavento;M.P. Manny;W. Hwang;S.H. Dhong

Year: 1991 | Conference Paper |

Submicrometer Si and Si-Ge epitaxial-base double-poly self-aligned bipolar transistors

T.C. Chen;E. Ganin;H. Stork;B. Meyerson;J.D. Cressler;J. Warnock;D. Harame;G. Patton;G.P. Li;C.T. Chuang;T.H. Ning

IEEE Transactions on Electron Devices
Year: 1991 | Volume: 38, Issue: 4 | Journal Article |
Cited by: Papers (7) | Patents (6)
The fabrication, device profiles, and electrical characteristics of epitaxial-base double-poly self-aligned bipolar transistors are presented. The intrinsic-base regions in the present device structures reside above the silicon surface and were formed using a boron-doped low-temperature epitaxially (LTE)-grown Si or Si-Ge layer to achieve a narrow intrinsic-base width (≤ 60 nm) and a low base pinc...Show More

Submicrometer Si and Si-Ge epitaxial-base double-poly self-aligned bipolar transistors

T.C. Chen;E. Ganin;H. Stork;B. Meyerson;J.D. Cressler;J. Warnock;D. Harame;G. Patton;G.P. Li;C.T. Chuang;T.H. Ning

Year: 1991 | Volume: 38, Issue: 4 | Journal Article |

Sub-15 ps gate delay with new AC-coupled active pull-down ECL circuit

K.-Y. Toh;J.D. Warnock;J.D. Cressler;K.A. Jenkins;D.A. Danner;T.-C. Chen

Proceedings of the 1991 Bipolar Circuits and Technology Meeting
Year: 1991 | Conference Paper |
Cited by: Papers (5)
An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f/sub T/ ion-implanted silicon bipolar technology. This circuit could be useful as an internal gate operating at low-power and as an I/O gate to drive a large capacitive load at high-power....Show More

Sub-15 ps gate delay with new AC-coupled active pull-down ECL circuit

K.-Y. Toh;J.D. Warnock;J.D. Cressler;K.A. Jenkins;D.A. Danner;T.-C. Chen

Year: 1991 | Conference Paper |

A 26 ps self-aligned epitaxial silicon base bipolar technology

J.H. Comfort;P.-F. Lu;D.D. Tang;T.-C. Chen;J.Y.-C. Sun;B.S. Meyerson;W. Lee;J. Warnock;J.D. Cressler;K.-Y. Toh;J.M. Cotte

Digest of Technical Papers.1990 Symposium on VLSI Technology
Year: 1990 | Conference Paper |
Cited by: Papers (8)
A self-aligned epitaxial base technology is presented which allows fabrication of advanced bipolar devices with 40 to 60 nm basewidths and implementation of novel profile design concepts. The viability of this technology for advanced bipolar circuits has been examined by fabricating ECL ring oscillators, thus demonstrating that fully scaled epi-base devices can be successfully integrated. Devices ...Show More

A 26 ps self-aligned epitaxial silicon base bipolar technology

J.H. Comfort;P.-F. Lu;D.D. Tang;T.-C. Chen;J.Y.-C. Sun;B.S. Meyerson;W. Lee;J. Warnock;J.D. Cressler;K.-Y. Toh;J.M. Cotte

Year: 1990 | Conference Paper |

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