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A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback
Zexin Wang;Lingxin Meng;Menglian Zhao;Mengyu Li;Shuang Song;Zhichao Tan
2025 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2025 | Conference Paper |
Level-crossing (LC) ADCs are superior choices for digitizing sparse input signals, which have short bursts of activity followed by long periods of silence. Monitored by a continuous-time (CT) comparator, the input signal is only processed after crossing a predefined voltage. This event-driven working scheme results in concentrated conversions solely during active periods, significantly reducing po...Show More
A 98.7/97.5 dB-DR 10/20 kHz-BWs Dual-Mode Continuous-Time Delta-Sigma ADC
Kaiquan Chen;Biao Wang;Yuhan Pan;Zhichao Tan;Guoxing Wang;Yong Lian;Liang Qi
IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025 | Early Access Article |
This work presents a highly compatible dual-mode continuous-time (CT) delta-sigma analog-to-digital converter (ADC) that can be applied to continuous or sample-by-sample acquisitions. According to different scenarios, based on a compact 3rd-order CT delta-sigma loop filter using a 17-level quantizer, it can be easily configured as either a CT delta-sigma modulator (DSM) or a CT incremental ADC (IA...Show More
Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range
IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025 | Early Access Article |
This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH ΔΣ ADC...Show More
A 12A 89.3% Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators
Shengdao Ren;Yukan Du;Menglian Zhao;Zhichao Tan;Chushan Li;Yong Ding;Wuhua Li;Wanyuan Qu
2025 IEEE International Solid-State Circuits Conference (ISSCC)
Year: 2025 | Conference Paper |
The ever-hungry computing needs for data centers and automotive applications require a large output current at sub-1 V voltages. On the other hand, the input voltage of power converters must be raised to ease the 12R loss on the system voltage bus. The high input voltage and large output current requirements impose significant challenges on the converter efficiency, density, and speed, which are a...Show More
Analysis and Design of a 16-bit Continuous-Time Incremental Delta-Sigma ADC
IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025 | Early Access Article |
This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-ΔΣ) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achiev...Show More
An 871 nW 96.2 dB SNDR Pipelined Second-Order Noise-Shaping SAR ADC Employing Charge-Efficient CLS-Assisted Residue Amplifier
Shan Zhang;Lingxin Meng;Zhaonan Lu;Shuang Song;Wanyuan Qu;Menglian Zhao;Zhichao Tan
This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue ampl...Show More
A High-Efficiency 12/1-V Dual-Path Series-Capacitor Converter With Low V⋅A Metric and Full Duty Range
Xu Yang;Linhu Zhao;Zhichao Tan;Menglian Zhao;Yong Ding;Wuhua Li;Wanyuan Qu
This article presents a dual-path series-capacitor (DPSC) converter with a voltage range of $9~{\sim }~16$ -V input to 1-V output. By forming a capacitive-current path with flying capacitors, the proposed DPSC converter alleviates both voltage and current stresses on both the inductor and switches, enhancing overall efficiency and achieving the lowest $V\cdot A$ metric for the switches. The pro...Show More
A 62.2dB SNDR Event-Driven Level-Crossing ADC With SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition
Mengyu Li;Yi Huo;Shuang Song;Wanyuan Qu;Le Ye;Menglian Zhao;Zhichao Tan
This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is...Show More
A 91.7dB-SNDR 5kHz BW 18.5μW PPD-based Single-OTA Zoom ADC using CLS-enhanced Inverter Amplifier
Yining Zhao;Zhaonan Lu;Shuang Song;Liang Zhao;Menglian Zhao;Zhichao Tan
2024 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
Year: 2024 | Conference Paper |
This paper presents a pseudo-pseudo-differential (PPD)--based single-OTA 2nd-order zoom ADC, which employs a 4-bit SAR conversion followed by a 2 nd-order $\Delta \Sigma$ modulator using a single-OTA. The PPD technique significantly minimizes the OTA noise at low frequencies. A CLS-enhanced cascode inverter is proposed as the OTA, boosting its DC gain to 75dB to meet structural requirements. The c...Show More
A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS
Yuekai Liu;Meng Guo;Yichen Jin;Yan Liu;Mingqiang Guo;Sai-Weng Sin;Zhichao Tan;Liang Qi
2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2024 | Conference Paper |
In recent years, Gigahertz-rate oversampled CT DSMs have been consistently explored to pursue a larger bandwidth (BW) [1] –[4]. Note that the usable oversampling ratio (OSR) is seriously limited (i.e. below 10) in those works owing to the restrained clock rate. A low OSR results in poor quantization efficiency, thus limiting the achievable dynamic range (DR). In such an ultra-low-OSR context, mult...Show More
A Power-Area Efficient New Merged Capacitor Switching Scheme for SAR ADC
Cong Wei;Rongshan Wei;Qikun Zhou;Lijie Huang;Xiaoqiang Lu;Zhichao Tan
2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2024 | Conference Paper |
This article introduces a power-area efficient new merged capacitor switching (NMCS) scheme for successive approximation register (SAR) analog-to-digital converters (ADCs). It addresses the drawback of conventional CDAC switching schemes, where energy is consumed with each decision. In this scheme, energy is consumed during the first decision, no energy is consumed during the second decision, and ...Show More
A 50kHz-BW 95.4dB-SNDR CT-DT Pipelined Noise-Shaping SAR ADC with Noise-Optimized Two-Stage Dynamic Amplifier
2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2024 | Conference Paper |
This article presents a highly energy-efficient CT-DT pipelined noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a closed-loop noise-optimized two-stage dynamic amplifier working as the residue amplifier (RA). The sampling-free capacitively-coupled 1st stage breaks the kT/C limit between the SNR and the input capacitor size, thus easing the buffer r...Show More
A 96dB DR 3.1GΩ Input Impedance CT-DT ΔΣ Readout Frontend with Level-Crossing Input Range Enhancement for Neural Recordings
Tian Yang;Mengyu Li;Shuang Song;Yiqi Chen;Zhaonan Lu;Shiwei Wang;Yongpeng Cheng;Zhichao Tan;Menglian Zhao
2024 IEEE Biomedical Circuits and Systems Conference (BioCAS)
Year: 2024 | Conference Paper |
This paper proposes a neural recording frontend with a level crossing (LC) style DR-enhancing loop, featuring fast transient response and a wide input range. A dual-Gm input stage together with a differential input single-ended output TIA is exploited, enabling energy efficient LC event detection. The LC capacitive DAC generates a voltage that follows the input, enhancing the DR. A current mode se...Show More
Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta-Sigma Modulator
IEEE Open Journal of the Solid-State Circuits Society
Year: 2024 | Early Access Article |
Cited by: Papers (1)
Low-voltage delta-sigma modulators have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage DT DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively-biased floating inverter amplifier is presented with detailed design consider...Show More
This article presents an embedded-friendly high-precision two-step noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) designed for sensor applications. By employing a continuous-time (CT) SAR to track the input signal, the design avoids the kT/C noise typically induced by sampling operations. This approach decouples the signal-to-noise ratio (SNR) from the...Show More
An Energy Efficient Amplifier with a Closed Loop Gm-Boosting Output Stage for Large Capacitive Loads Achieving 686,685 MHz▪pF/mA IFoMs
Zhenan Xu;Shuang Song;Dehong Wang;Mengyu Li;Qiuyang Lin;Mingsheng Xu;Wanyuan Qu;Zhichao Tan;Menglian Zhao
2024 IEEE European Solid-State Electronics Research Conference (ESSERC)
Year: 2024 | Conference Paper |
This paper proposed a low-power two-stage amplifier for large capacitive load driving. A closed-loop gmboosted (CLGB) output stage is exploited to reduce the output resistance and thus makes the output pole non-dominant. This allows an internally defined dominant pole, resulting in a high gain-bandwidth (GBW) without using compensation capacitor. Meanwhile, a current-reuse stacked (CRS) slew rate ...Show More
A 20kHz 87.2dB SNDR 12.1µW NS SAR ADC Based on Quantization-Error-Matched RLSB-First Algorithm
2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS)
Year: 2024 | Conference Paper |
Most noise shaping (NS) SAR ADCs still use the same control algorithm as Nyquist SAR ADC. Noticing the slow-varying input under oversampling, this paper proposed a new algorithm named quantization-error-matched RLSB-first to improve the switching efficiency. Compared with the VCM-based algorithm, the proposed algorithm saves 87.3 % switching power consumption in a 1st order NS SAR under an OSR of ...Show More
A 12.9-ENOB 50.6 fJ/conv.step Time-Amplitude Aligned Level-Crossing SAR ADC
2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
This paper presents a time-amplitude aligned level-crossing (LC) SAR ADC for sparse signal acquisition. In conventional level-crossing ADCs, misalignment between time and amplitude induces significant error during interpolation. A level-crossing SAR is first proposed in this paper to effectively cancel the misalignment. Triggered by a 16-level continuous-time LC detector, the quantization is perfo...Show More
Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective
Shuang Song;Dehong Wang;Mengyu Li;Siyao Cao;Feijun Zheng;Kai Huang;Zhichao Tan;Sijun Du;Menglian Zhao
Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, inc...Show More
A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA
Weiqiang Chen;Lingxin Meng;Yining Zhao;Menglian Zhao;Zhichao Tan
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
This work proposes a floating-inverter-amplifier (FIA) based high-precision dynamic zoom ADC for low-voltage battery-powered applications. A capacitive biasing technique is proposed to reboot the FIA under low voltages, which enables the FIA to operate under a near-threshold supply voltage. Furthermore, correlated-level-shifting (CLS) is employed to boost the DC gain of the FIA to 51 dB. Simulated...Show More
An SRAM Compute-In-Memory Macro Based on Direct Coupling SAR ADC and DAC Reuse
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2024 | Conference Paper |
Deep neural networks (DNNs) can be implemented in low-power, small-area systems using compute-in-memory (CIM). This study proposes a CIM MAC macro based on 8T SRAM and a 5-bit Successive Analog-to-Digital Data Converter (SAR ADC) readout circuit to execute low-power and highspeed calculations. This architecture has no buffers between the low-power SAR ADC and the pre-stage. The SAR ADC’s capacitor...Show More
A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC
2024 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2024 | Conference Paper |
Cited by: Papers (3)
The rapid progress of smart sensors and biomedical front-ends is summoning high-precision, high-energy-efficiency ADCs. To be embedded-friendly, properties like easily driven, adaptive bandwidth, and feasible clock generation cost are also favorable. In recent years, noise-shaping (NS) SARs have gained a great vogue for their fully dynamic operation and high energy efficiency [1]–[3]. Although imp...Show More
A 188.6-μW Continuous-time Incremental Delta-Sigma ADC with Extended Counting achieving 95.2-dB SNDR and 175.4-dB FoMSNDR
2024 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Delta-sigma $(\Delta\Sigma)$ analog-to-digital converters (ADCs) are well-known for oversampling and noise-shaping techniques to achieve high resolution and good power efficiency. However, free-running $\Delta\Sigma$ ADCs are dynamic systems with memory that cannot offer one-to-one mapping between input and output samples. Therefore, incremental delta-sigma $(\vert \Delta\Sigma)$ ADCs, resetting t...Show More
An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA
Shan Zhang;Lingxin Meng;Zhaonan Lu;Wanyuan Qu;Shuang Song;Menglian Zhao;Zhichao Tan
2024 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2024 | Conference Paper |
Cited by: Papers (3)
High-precision and ultra-low-power (ULP) ADCs have received significant demand recently due to their critical roles in biomedical or Internet-of-things products. However, achieving a 16-bit resolution with sub-micro-watt $(< 1\mu\mathrm{W})$ ADCs remains a significant challenge, serving as a bottleneck for ULP signal acquisition systems. Noise-shaping (NS) SAR ADCs can effectively reduce in-band q...Show More
A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs
This article presents a switched-capacitor (SC) delta–sigma modulator (DSM) for low-power and high-precision applications. With a 5-bit noise-shaping (NS) successive-approximation-register (NSSAR) quantizer embedded in the 2nd-order loop filter, the system achieves a stable 3rd-order noise transfer function (NTF) without coefficient scaling. Partial feedback with digital filters is adopted, which ...Show More
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