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Heoun-Taek Lim - IEEE Xplore Author Profile
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Heoun-Taek Lim

Also published under: Heaun-Taek Lim, Heoun-taek Lim

Publications
4
Citations
260
Publications by Year
20182020
Co-Authors:
Image of author Heoun-Taek Lim

Heoun-Taek Lim

Also published under: Heaun-Taek Lim, Heoun-taek Lim

Affiliation

Image and Video Systems Lab
School of Electrical Engineering
Korea Advanced Institute of Science and Technology, Daejeon, South Korea

Publication Topics

Biography

Heoun-Taek Lim received the B.S. and M.S. degrees from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2015 and 2018, respectively. His research interests include deep learning, virtual reality, 3D image/video processing, human 3D/VR perception, and visual quality assessment.(Based on document published on 10 February 2019).
Publications
4
Citations
260
Publications by Year
20182020
Co-Authors:
Author's Published Works

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A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA

Gabriele Zanoletti;Gabriele Bè;Michele Rocco;Luca Ricci;Alessia Ceroni;Salvatore Levantino;Andrea Leonardo Lacaita;Luca Bertulessi;Andrea Bonfanti;Carlo Samori

2025 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2025 | Conference Paper |
Combining the noise-shaping (NS) technique with the SAR converter enables high resolution while maintaining state-of-the-art power efficiency and minimal area occupation [1]. However, the performance of existing NS SAR ADCs drops significantly for bandwidths higher than a few MHz, making the NS SAR unattractive for high-speed applications such as wireless communications. Single-core wideband solut...Show More

A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA

Gabriele Zanoletti;Gabriele Bè;Michele Rocco;Luca Ricci;Alessia Ceroni;Salvatore Levantino;Andrea Leonardo Lacaita;Luca Bertulessi;Andrea Bonfanti;Carlo Samori

Year: 2025 | Conference Paper |

A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk

Luca Ricci;Gabriele Bè;Michele Rocco;Lorenzo Scaletti;Gabriele Zanoletti;Luca Bertulessi;Andrea L. Lacaita;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

IEEE Journal of Solid-State Circuits
Year: 2025 | Volume: 60, Issue: 2 | Journal Article |
Cited by: Papers (3)
Time-interleaved (TI) analog-to-digital converters (ADCs) are an established architecture, but fundamental problems still exist that prevent replicating the performance of each sub-ADC to the overall TI ADC. This article presents different techniques to overcome the main challenges in implementing an interleaved converter: 1) driving the ADC with sufficient linearity and bandwidth; 2) avoiding the...Show More

A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk

Luca Ricci;Gabriele Bè;Michele Rocco;Lorenzo Scaletti;Gabriele Zanoletti;Luca Bertulessi;Andrea L. Lacaita;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

Year: 2025 | Volume: 60, Issue: 2 | Journal Article |

A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization

Gabriele Zanoletti;Lorenzo Scaletti;Gabriele Bè;Luca Ricci;Michele Rocco;Luca Bertulessi;Carlo Samori;Andrea Bonfanti

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2024 | Volume: 71, Issue: 3 | Journal Article |
Cited by: Papers (1)
This brief presents a linearity enhancement method, named charge linearization technique (CLT), for top-plate input successive approximation register (SAR) data converters. The proposed CLT removes the linearity degradation due to the non-linear parasitic capacitance of the comparator. Consequently, the constraint on the size of the comparator is relieved. An 11-bit redundant SAR converter featuri...Show More

A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization

Gabriele Zanoletti;Lorenzo Scaletti;Gabriele Bè;Luca Ricci;Michele Rocco;Luca Bertulessi;Carlo Samori;Andrea Bonfanti

Year: 2024 | Volume: 71, Issue: 3 | Journal Article |

A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity

Lorenzo Scaletti;Luca Bertulessi;Andrea Cristofoli;Andrea Bonfanti

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)
Year: 2023 | Conference Paper |
Cited by: Papers (4)
In this paper, we present a novel input buffer based on the push-pull architecture for an 11-bit 2-GS/s 8x time-interleaved ADC. The proposed buffer features an auxiliary follower which is used to drive the body terminals of the main push-pull output transistors, removing their non-linear contribution at the output node, with a negligible overhead in terms of power consumption. The ADC features a ...Show More

A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity

Lorenzo Scaletti;Luca Bertulessi;Andrea Cristofoli;Andrea Bonfanti

Year: 2023 | Conference Paper |

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS

Luca Ricci;Lorenzo Scaletti;Gabriele Bè;Michele Rocco;Luca Bertulessi;Salvatore Levantino;Andrea Lacaita;Carlo Samori;Andrea Bonfanti

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Year: 2023 | Conference Paper |
Cited by: Papers (5)
A 2GS/s 11b 8x-interleaved ADC is presented where flipped-voltage-follower-based reference buffers attenuate channel interactions and a set of on-chip background digital calibrations mitigate channel mismatches. A high-linearity input buffer is included which does not degrade ADC performances. Implemented in a 28nm CMOS technology, the ADC achieves 57.3dB SNDR and 69.9dB SFDR close to the Nyquist ...Show More

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS

Luca Ricci;Lorenzo Scaletti;Gabriele Bè;Michele Rocco;Luca Bertulessi;Salvatore Levantino;Andrea Lacaita;Carlo Samori;Andrea Bonfanti

Year: 2023 | Conference Paper |

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

Francesco Tesolin;Simone M. Dartizio;Francesco Buccoleri;Alessio Santiccioli;Luca Bertulessi;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

IEEE Journal of Solid-State Circuits
Year: 2023 | Volume: 58, Issue: 9 | Journal Article |
Cited by: Papers (8)
An LO phase-shifting system based on digital fractional- ${N}$ bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to-time converter (DTC) nonlinearities. Synchro...Show More

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

Francesco Tesolin;Simone M. Dartizio;Francesco Buccoleri;Alessio Santiccioli;Luca Bertulessi;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

Year: 2023 | Volume: 58, Issue: 9 | Journal Article |

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Giacomo Castoro;Simone M. Dartizio;Francesco Tesolin;Francesco Buccoleri;Michele Rossoni;Dmytro Cherniak;Luca Bertulessi;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

2023 IEEE International Solid-State Circuits Conference (ISSCC)
Year: 2023 | Conference Paper |
Cited by: Papers (20)
The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-time-converter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of t...Show More

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Giacomo Castoro;Simone M. Dartizio;Francesco Tesolin;Francesco Buccoleri;Michele Rossoni;Dmytro Cherniak;Luca Bertulessi;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

Year: 2023 | Conference Paper |

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Francesco Buccoleri;Simone M. Dartizio;Francesco Tesolin;Luca Avallone;Alessio Santiccioli;Agata Iesurum;Giovanni Steffan;Dmytro Cherniak;Luca Bertulessi;Andrea Bevilacqua;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

IEEE Journal of Solid-State Circuits
Year: 2023 | Volume: 58, Issue: 3 | Journal Article |
Cited by: Papers (8)
This work presents a low-jitter and low out-of-band noise two-core fractional- $N$ digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of th...Show More

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Francesco Buccoleri;Simone M. Dartizio;Francesco Tesolin;Luca Avallone;Alessio Santiccioli;Agata Iesurum;Giovanni Steffan;Dmytro Cherniak;Luca Bertulessi;Andrea Bevilacqua;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

Year: 2023 | Volume: 58, Issue: 3 | Journal Article |

Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs

Luca Ricci;Lorenzo Scaletti;Gabriele Bè;Luca Bertulessi;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
This paper analyses for the first time from a quantitative standpoint the effectiveness of redundancy in successive approximation register (SAR) analog-to-digital converters (ADCs) that employ the conventional and monotonic switching algorithms. It is shown that the redundancy tolerance window is one-sided in the case of conventional switching algorithm, thus only underestimations of the input sig...Show More

Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs

Luca Ricci;Lorenzo Scaletti;Gabriele Bè;Luca Bertulessi;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

Year: 2022 | Conference Paper |

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters

Lorenzo Scaletti;Gabriele Bè;Angelo Parisi;Luca Bertulessi;Luca Ricci;Mario Mercandelli;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
In this work, a 12-bit, 150-MS/s, 13-steps redundant asynchronous SAR ADC achieving better than 63-dB SNDR and 72-dB SFDR with a 100-MHz Equivalent Resolution Bandwidth (ERBW) is presented. To achieve a high conversion rate without impairing accuracy, the implemented ADC features a custom sub-fF unit capacitance with mismatch calibration in the digital domain, a sub-radix-2 CDAC which introduces r...Show More

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters

Lorenzo Scaletti;Gabriele Bè;Angelo Parisi;Luca Bertulessi;Luca Ricci;Mario Mercandelli;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

Year: 2022 | Conference Paper |

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

Gabriele Bè;Angelo Parisi;Luca Bertulessi;Luca Ricci;Lorenzo Scaletti;Mario Mercandelli;Andrea L. Lacaita;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2022 | Volume: 69, Issue: 9 | Journal Article |
Cited by: Papers (10)
This brief presents a 12-bit successive approximation register (SAR)-based time-interleaved (TI) analog-to-digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrat...Show More

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

Gabriele Bè;Angelo Parisi;Luca Bertulessi;Luca Ricci;Lorenzo Scaletti;Mario Mercandelli;Andrea L. Lacaita;Salvatore Levantino;Carlo Samori;Andrea Bonfanti

Year: 2022 | Volume: 69, Issue: 9 | Journal Article |

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

Francesco Buccoleri;Simone M. Dartizio;Francesco Tesolin;Luca Avallone;Alessio Santiccioli;Agata Iesurum;Giovanni Steffan;Andrea Bevilacqua;Luca Bertulessi;Dmytro Cherniak;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

2022 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2022 | Conference Paper |
Cited by: Papers (4)
Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-co...Show More

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

Francesco Buccoleri;Simone M. Dartizio;Francesco Tesolin;Luca Avallone;Alessio Santiccioli;Agata Iesurum;Giovanni Steffan;Andrea Bevilacqua;Luca Bertulessi;Dmytro Cherniak;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

Year: 2022 | Conference Paper |

A Digital PLL With Multitap LMS-Based Bandwidth Control

Mario Mercandelli;Luca Bertulessi;Carlo Samori;Salvatore Levantino

IEEE Solid-State Circuits Letters
Year: 2022 | Volume: 5 | Journal Article |
Cited by: Papers (4)
Automatic bandwidth control based on least mean-square adaptive filters has been demonstrated to desensitize the loop gain of a phase-locked loop (PLL) from process spreads, environmental variations, and channel frequency. This work extends this concept to low-jitter designs that adopt aggressive out-of-band filtering, by introducing multitap adaptive filtering. The method requires no injection of...Show More

A Digital PLL With Multitap LMS-Based Bandwidth Control

Mario Mercandelli;Luca Bertulessi;Carlo Samori;Salvatore Levantino

Year: 2022 | Volume: 5 | Journal Article |

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise

Luca Bertulessi;Dmytro Cherniak;Mario Mercandelli;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2022 | Volume: 69, Issue: 5 | Journal Article |
Cited by: Papers (9)
This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digi...Show More

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise

Luca Bertulessi;Dmytro Cherniak;Mario Mercandelli;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino

Year: 2022 | Volume: 69, Issue: 5 | Journal Article |

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

Mario Mercandelli;Alessio Santiccioli;Angelo Parisi;Luca Bertulessi;Dmytro Cherniak;Andrea L. Lacaita;Carlo Samori;Salvatore Levantino

IEEE Journal of Solid-State Circuits
Year: 2022 | Volume: 57, Issue: 2 | Journal Article |
Cited by: Papers (32)
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which prov...Show More

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

Mario Mercandelli;Alessio Santiccioli;Angelo Parisi;Luca Bertulessi;Dmytro Cherniak;Andrea L. Lacaita;Carlo Samori;Salvatore Levantino

Year: 2022 | Volume: 57, Issue: 2 | Journal Article |

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio;Francesco Tesolin;Mario Mercandelli;Alessio Santiccioli;Abanob Shehata;Saleh Karman;Luca Bertulessi;Francesco Buccoleri;Luca Avallone;Angelo Parisi;Andrea L. Lacaita;Michael P. Kennedy;Carlo Samori;Salvatore Levantino

IEEE Journal of Solid-State Circuits
Year: 2022 | Volume: 57, Issue: 6 | Journal Article |
Cited by: Papers (20)
This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core ...Show More

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio;Francesco Tesolin;Mario Mercandelli;Alessio Santiccioli;Abanob Shehata;Saleh Karman;Luca Bertulessi;Francesco Buccoleri;Luca Avallone;Angelo Parisi;Andrea L. Lacaita;Michael P. Kennedy;Carlo Samori;Salvatore Levantino

Year: 2022 | Volume: 57, Issue: 6 | Journal Article |

A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter

Mario Mercandelli;Luca Bertulessi;Carlo Samori;Salvatore Levantino

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
Digital PLLs (DPLLs) have demonstrated to be a promising candidate to implement frequency synthesizers in wireless transceivers, thanks to their scaling-friendly architecture and to the possibility of implementing powerful background adaptive calibration algorithms to compensate the system non-idealities. The combination of these features leads to an inherently faster time-to-market than tradition...Show More

A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter

Mario Mercandelli;Luca Bertulessi;Carlo Samori;Salvatore Levantino

Year: 2021 | Conference Paper |

Digital PLLs: the modern timing reference for radar and communication systems

Carlo Samori;Luca Bertulessi

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Year: 2021 | Conference Paper |
Cited by: Papers (5)
Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS....Show More

Digital PLLs: the modern timing reference for radar and communication systems

Carlo Samori;Luca Bertulessi

Year: 2021 | Conference Paper |

Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators

A. Parisi;F. Tesolin;M. Mercandelli;L. Bertulessi;A. L. Lacaita

IEEE Microwave and Wireless Components Letters
Year: 2021 | Volume: 31, Issue: 9 | Journal Article |
Cited by: Papers (3)
This work presents a very compact self-biasing dynamic startup circuit for class-C voltage-controlled oscillators (VCOs). Using a referenceless nonlinear inverting stage, the solution has been implemented in a 28-nm CMOS technology 14-GHz oscillator, leading to a VCO startup time better than 20 ns, at par with the fastest startup circuits in literature, with an extremely compact area of 0.003 mm2.Show More

Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators

A. Parisi;F. Tesolin;M. Mercandelli;L. Bertulessi;A. L. Lacaita

Year: 2021 | Volume: 31, Issue: 9 | Journal Article |

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Alessio Santiccioli;Mario Mercandelli;Luca Bertulessi;Angelo Parisi;Dmytro Cherniak;Andrea L. Lacaita;Carlo Samori;Salvatore Levantino

IEEE Journal of Solid-State Circuits
Year: 2020 | Volume: 55, Issue: 12 | Journal Article |
Cited by: Papers (61)
This article presents a fractional-N frequency synthesizer architecture that is able to overcome the limitations of conventional bang-bang phase-locked loops. A digital frequencyerror recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jit...Show More

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Alessio Santiccioli;Mario Mercandelli;Luca Bertulessi;Angelo Parisi;Dmytro Cherniak;Andrea L. Lacaita;Carlo Samori;Salvatore Levantino

Year: 2020 | Volume: 55, Issue: 12 | Journal Article |

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