Loading [a11y]/accessibility-menu.js
Sangram More - IEEE Xplore Author Profile
Subscribe
ADVANCED SEARCH

Author details

< Back

Sangram More

Also published under: Sangram S. More

Publications
4
Citations
2
Publications by Year
20172022
Co-Authors:
Headshot silhouette indicating that no photo is available for this author

Sangram More

Also published under: Sangram S. More

Affiliation

Dept. of E&TC
College of Engineering Pune & SCTR's PICT
Pune, India

Publication Topics

Biography

Sangram S. More received Masters's degree in Electronics &Telecommunication Engineering from SYMBIOSIS International University Pune, 2015. Currently he is working as an Assistant Professor in Electronics Engineering, Maharashtra Institute of Technology (MITAOE), Pune and doing research on underwater communication at Communication Laboratory, Defence Institute of Advanced Technology, Pune. His current areas of interest include Acoustic Communication, Wireless Sensor Networks and Wireless Communication.(Based on document published on 3 January 2019).
Publications
4
Citations
2
Publications by Year
20172022
Co-Authors:
Author's Published Works

Showing 1-25 of 53 results

  • Sort

Filter Results

Show

Sort By

Results

Toward a Universal Cryptographic Accelerator

Srinivas Devadas;Daniel Sanchez

Computer
Year: 2025 | Volume: 58, Issue: 1 | Magazine Article |
Cyberphysical systems have disseminated devices that can be untrustworthy or compromised. Nevertheless, the privacy and integrity of computation and data can be guaranteed through cryptographic protocols. We address the computational burden posed by cryptography, and argue for a synergistic approach of designing programmable hardware accelerators for cryptography, followed by tailoring cryptograph...Show More

Toward a Universal Cryptographic Accelerator

Srinivas Devadas;Daniel Sanchez

Year: 2025 | Volume: 58, Issue: 1 | Magazine Article |

Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures

Hyun Ryong Lee;Daniel Sanchez

2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2024 | Conference Paper |
Sparse data structures like hash tables, trees, or compressed tensors are ubiquitous, but operations on these structures are expensive and inefficient on current systems. Prior work has proposed hardware acceleration for these operations, but these techniques have two key shortcomings: they limit the types of data structures they support, and they focus on reads but do not support fine-grained upd...Show More

Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures

Hyun Ryong Lee;Daniel Sanchez

Year: 2024 | Conference Paper |

Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory

Axel Feldmann;Courtney Golden;Yifan Yang;Joel S. Emer;Daniel Sanchez

2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2024 | Conference Paper |
Solving sparse systems of linear equations is a fundamental primitive in many numeric algorithms. Iterative solvers provide an efficient way of solving large, highly sparse systems. However, iterative solvers are inefficient on existing architectures because they perform computations with (1) poor short-term reuse, which causes frequent off-chip memory traffic; and (2) challenaing data dependences...Show More

Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory

Axel Feldmann;Courtney Golden;Yifan Yang;Joel S. Emer;Daniel Sanchez

Year: 2024 | Conference Paper |

Accelerating Zero-Knowledge Proofs Through Hardware-Algorithm Co-Design

Nikola Samardzic;Simon Langowski;Srinivas Devadas;Daniel Sanchez

2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Zero-Knowledge Proofs (ZKPs) are a cryptographic tool that enables one party (a prover) to prove to another (a verifier) that a statement is true, without requiring the prover to disclose any data to the verifier. ZKPs have many use cases, such as letting clients delegate computation to servers with cryptographic correctness guarantees, while enabling the server to use secret data in these computa...Show More

Accelerating Zero-Knowledge Proofs Through Hardware-Algorithm Co-Design

Nikola Samardzic;Simon Langowski;Srinivas Devadas;Daniel Sanchez

Year: 2024 | Conference Paper |

Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications

Yifan Yang;Joel S. Emer;Daniel Sanchez

2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)
Year: 2024 | Conference Paper |
Cited by: Papers (2)
Accelerating matrix multiplication is crucial to achieve high performance in many application domains, including neural networks, graph analytics, and scientific computing. These applications process matrices with a wide range of sparsities, from completely dense to highly sparse. Ideally, a single accelerator should handle matrices of all sparsity levels well. However, prior matrix multiplication...Show More

Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications

Yifan Yang;Joel S. Emer;Daniel Sanchez

Year: 2024 | Conference Paper |

Accelerating RTL Simulation with Hardware-Software Co-Design

Fares Elsabbagh;Shabnam Sheikhha;Victor A. Ying;Quan M. Nguyen;Joel S. Emer;Daniel Sanchez

2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent.We present ASH, a parallel architecture tailored to simulation workloads. ASH consists of a tightly codesigned hardware architecture and compiler for RTL simulatio...Show More

Accelerating RTL Simulation with Hardware-Software Co-Design

Fares Elsabbagh;Shabnam Sheikhha;Victor A. Ying;Quan M. Nguyen;Joel S. Emer;Daniel Sanchez

Year: 2023 | Conference Paper |

Spatula: A Hardware Accelerator for Sparse Matrix Factorization

Axel Feldmann;Daniel Sanchez

2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
Solving sparse systems of linear equations is a crucial component in many science and engineering problems, like simulating physical systems. Sparse matrix factorization dominates a large class of these solvers. Efficient factorization algorithms have two key properties that make them challenging for existing architectures: they consist of small tasks that are structured and compute-intensive, and...Show More

Spatula: A Hardware Accelerator for Sparse Matrix Factorization

Axel Feldmann;Daniel Sanchez

Year: 2023 | Conference Paper |

ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining

Yifan Yang;Joel S. Emer;Daniel Sanchez

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Year: 2023 | Conference Paper |
Cited by: Papers (14)
Sparse CNNs dramatically reduce computation and storage costs over dense ones. But sparsity also makes CNNs more data-intensive, as each value is reused fewer times. Thus, current sparse CNN accelerators, which process one layer at a time, are bottlenecked by memory traffic.We present ISOSceles, a new sparse CNN accelerator that dramatically reduces data movement through inter-layer pipelining: ov...Show More

ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining

Yifan Yang;Joel S. Emer;Daniel Sanchez

Year: 2023 | Conference Paper |

Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism

Quan M. Nguyen;Daniel Sanchez

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
Irregular applications are increasingly common in diverse domains, like graph analytics and sparse linear algebra. Accelerating these applications is challenging because of their unpredictable data reuse and control flow. Recent work has proposed hardware support for fine-grain pipeline parallelism, hiding long latencies by decoupling irregular applications into pipeline stages. However, this prio...Show More

Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism

Quan M. Nguyen;Daniel Sanchez

Year: 2023 | Conference Paper |

Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets

Hyun Ryong Lee;Daniel Sanchez

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
Benchmarks that closely match the behavior of production workloads are crucial to design and provision computer systems. However, current approaches fall short: First, open-source benchmarks use public datasets that cause different behavior from production workloads. Second, blackbox workload cloning techniques generate synthetic code that imitates the target workload, but the resulting program fa...Show More

Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets

Hyun Ryong Lee;Daniel Sanchez

Year: 2022 | Conference Paper |

An Architecture to Accelerate Computation on Encrypted Data

Axel Feldmann;Nikola Samardzic;Aleksandar Krastev;Srinivas Devadas;Ron Dreslinski;Chris Peikert;Daniel Sanchez

IEEE Micro
Year: 2022 | Volume: 42, Issue: 4 | Magazine Article |
Fully homomorphic encryption (FHE) allows computing on encrypted data, enabling secure offloading of computation to untrusted servers. Though it provides ideal security, FHE is prohibitively expensive when executed in software. These overheads are a major barrier to FHE's widespread adoption. We present F1, the first FHE accelerator that is capable of executing full FHE programs. F1 builds on an i...Show More

An Architecture to Accelerate Computation on Encrypted Data

Axel Feldmann;Nikola Samardzic;Aleksandar Krastev;Srinivas Devadas;Ron Dreslinski;Chris Peikert;Daniel Sanchez

Year: 2022 | Volume: 42, Issue: 4 | Magazine Article |

Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures

Ajay Brahmakshatriya;Emily Furst;Victor A. Ying;Claire Hsu;Changwan Hong;Max Ruttenberg;Yunming Zhang;Dai Cheol Jung;Dustin Richmond;Michael B. Taylor;Julian Shun;Mark Oskin;Daniel Sanchez;Saman Amarasinghe

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
Year: 2021 | Conference Paper |
Cited by: Papers (7)
We live in a new Cambrian Explosion of hardware devices. The end of conventional processor scaling has driven research and industry practice to explore a new generation of approaches. The old DNA of architecture design, including vectors, threads, shared or private memories, coherence or message passing, dataflow or von Neumann execution, are hybridized together in new and exciting ways. Each new ...Show More

Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures

Ajay Brahmakshatriya;Emily Furst;Victor A. Ying;Claire Hsu;Changwan Hong;Max Ruttenberg;Yunming Zhang;Dai Cheol Jung;Dustin Richmond;Michael B. Taylor;Julian Shun;Mark Oskin;Daniel Sanchez;Saman Amarasinghe

Year: 2021 | Conference Paper |

SpZip: Architectural Support for Effective Data Compression In Irregular Applications

Yifan Yang;Joel S. Emer;Daniel Sanchez

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
Year: 2021 | Conference Paper |
Cited by: Papers (17)
Irregular applications, such as graph analytics and sparse linear algebra, exhibit frequent indirect, data-dependent accesses to single or short sequences of elements that cause high main memory traffic and limit performance. Data compression is a promising way to accelerate irregular applications by reducing memory traffic. However, software compression adds substantial overheads, and prior hardw...Show More

SpZip: Architectural Support for Effective Data Compression In Irregular Applications

Yifan Yang;Joel S. Emer;Daniel Sanchez

Year: 2021 | Conference Paper |

Leaking Secrets Through Compressed Caches

Po-An Tsai;Andres Sanchez;Christopher W. Fletcher;Daniel Sanchez

IEEE Micro
Year: 2021 | Volume: 41, Issue: 3 | Magazine Article |
Cited by: Papers (1)
We offer the first security analysis of cache compression, a promising architectural technique that is likely to appear in future mainstream processors. We find that cache compression has novel security implications because the compressibility of a cache line reveals information about its contents. Compressed caches introduce a new side channel that is especially insidious, as simply storing data ...Show More

Leaking Secrets Through Compressed Caches

Po-An Tsai;Andres Sanchez;Christopher W. Fletcher;Daniel Sanchez

Year: 2021 | Volume: 41, Issue: 3 | Magazine Article |

Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism

Quan M. Nguyen;Daniel Sanchez

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2020 | Conference Paper |
Cited by: Papers (19)
Applications with irregular memory accesses and control flow, such as graph algorithms and sparse linear algebra, use high-performance cores very poorly and suffer from dismal IPC. Instruction latencies are so large that even SMT cores running multiple data-parallel threads suffer poor utilization.We find that irregular applications have abundant pipeline parallelism that can be used to boost util...Show More

Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism

Quan M. Nguyen;Daniel Sanchez

Year: 2020 | Conference Paper |

T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware

Victor A. Ying;Mark C. Jeffrey;Daniel Sanchez

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
Year: 2020 | Conference Paper |
Cited by: Papers (21)
Multicores are now ubiquitous, but programmers still write sequential code. Speculative parallelization is an enticing approach to parallelize code while retaining the ease of sequential programming, making parallelism pervasive. However, prior speculative parallelizing compilers and architectures achieved limited speedups due to high costs of recovering from misspeculation and hardware scalabilit...Show More

T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware

Victor A. Ying;Mark C. Jeffrey;Daniel Sanchez

Year: 2020 | Conference Paper |

Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling

Anurag Mukkara;Nathan Beckmann;Maleen Abeydeera;Xiaosong Ma;Daniel Sanchez

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2018 | Conference Paper |
Graph processing is increasingly bottlenecked by main memory accesses. On-chip caches are of little help because the irregular structure of graphs causes seemingly random memory references. However, most real-world graphs offer significant potential locality—it is just hard to predict ahead of time. In practice, graphs have well-connected regions where relatively few vertices share edges with many...Show More

Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling

Anurag Mukkara;Nathan Beckmann;Maleen Abeydeera;Xiaosong Ma;Daniel Sanchez

Year: 2018 | Conference Paper |

Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

Po-An Tsai;Changping Chen;Daniel Sanchez

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2018 | Conference Paper |
Cited by: Papers (22)
Conventional multicores rely on deep cache hierarchies to reduce data movement. Recent advances in die stacking have enabled near-data processing (NDP) systems that reduce data movement by placing cores close to memory. NDP cores enjoy cheaper memory accesses and are more area-constrained, so they use shallow cache hierarchies instead. Since neither shallow nor deep hierarchies work well for all a...Show More

Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

Po-An Tsai;Changping Chen;Daniel Sanchez

Year: 2018 | Conference Paper |

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism

Mark C. Jeffrey;Victor A. Ying;Suvinay Subramanian;Hyun Ryong Lee;Joel Emer;Daniel Sanchez

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2018 | Conference Paper |
Cited by: Papers (7)
Multicore systems should support both speculative and non-speculative parallelism. Speculative parallelism is easy to use and is crucial to scale many challenging applications, while non-speculative parallelism is more efficient and allows parallel irrevocable actions (e.g., parallel I/O). Unfortunately, prior techniques are far from this goal. Hardware transactional memory (HTM) systems support s...Show More

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism

Mark C. Jeffrey;Victor A. Ying;Suvinay Subramanian;Hyun Ryong Lee;Joel Emer;Daniel Sanchez

Year: 2018 | Conference Paper |

Rethinking the Memory Hierarchy for Modern Languages

Po-An Tsai;Yee Ling Gan;Daniel Sanchez

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2018 | Conference Paper |
Cited by: Papers (13)
We present Hotpads, a new memory hierarchy designed from the ground up for modern, memory-safe languages like Java, Go, and Rust. Memory-safe languages hide the memory layout from the programmer. This prevents memory corruption bugs and enables automatic memory management. Hotpads extends the same insight to the memory hierarchy: it hides the memory layout from software and takes control over it, ...Show More

Rethinking the Memory Hierarchy for Modern Languages

Po-An Tsai;Yee Ling Gan;Daniel Sanchez

Year: 2018 | Conference Paper |

KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores

Nosayba El-Sayed;Anurag Mukkara;Po-An Tsai;Harshad Kasture;Xiaosong Ma;Daniel Sanchez

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Year: 2018 | Conference Paper |
Cache partitioning is now available in commercial hardware. In theory, software can leverage cache partitioning to use the last-level cache better and improve performance. In practice, however, current systems implement way-partitioning, which offers a limited number of partitions and often hurts performance. These limitations squander the performance potential of smart cache management. We presen...Show More

KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores

Nosayba El-Sayed;Anurag Mukkara;Po-An Tsai;Harshad Kasture;Xiaosong Ma;Daniel Sanchez

Year: 2018 | Conference Paper |

Leveraging Hardware Caches for Memoization

Guowei Zhang;Daniel Sanchez

IEEE Computer Architecture Letters
Year: 2018 | Volume: 17, Issue: 1 | Journal Article |
Cited by: Papers (25)
Memoization improves performance and saves energy bycaching and reusing the outputs of repetitive computations. Prior work has proposed software and hardware memoization techniques, but both have significant drawbacks. Software memoization suffers from high runtime overheads, and is thus limited to long computations. Conventional hardware memoization techniques achieve low overheads and can memoiz...Show More

Leveraging Hardware Caches for Memoization

Guowei Zhang;Daniel Sanchez

Year: 2018 | Volume: 17, Issue: 1 | Journal Article |

Understanding Object-level Memory Access Patterns Across the Spectrum

Xu Ji;Chao Wang;Nosayba El-Sayed;Xiaosong Ma;Youngjae Kim;Sudharshan S. Vazhkudai;Wei Xue;Daniel Sanchez

SC17: International Conference for High Performance Computing, Networking, Storage and Analysis
Year: 2017 | Conference Paper |
Cited by: Papers (1)
Memory accesses limit the performance and scalability of countless applications. Many design and optimization efforts will benefit from an in-depth understanding of memory access behavior, which is not offered by extant access tracing and profiling methods.In this paper, we adopt a holistic memory access profiling approach to enable a better understanding of program-system memory interactions. We ...Show More

Understanding Object-level Memory Access Patterns Across the Spectrum

Xu Ji;Chao Wang;Nosayba El-Sayed;Xiaosong Ma;Youngjae Kim;Sudharshan S. Vazhkudai;Wei Xue;Daniel Sanchez

Year: 2017 | Conference Paper |

Fractal: An execution model for fine-grain nested speculative parallelism

Suvinay Subramanian;Mark C. Jeffrey;Maleen Abeydeera;Hyun Ryong Lee;Victor A. Ying;Joel Emer;Daniel Sanchez

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA)
Year: 2017 | Conference Paper |
Cited by: Papers (8)
The following topics are dealt with: microprocessor chips; cache storage; multiprocessing systems; DRAM chips; storage management; graphics processing units; power aware computing; parallel architectures; memory architecture; and integrated circuit design.Show More

Fractal: An execution model for fine-grain nested speculative parallelism

Suvinay Subramanian;Mark C. Jeffrey;Maleen Abeydeera;Hyun Ryong Lee;Victor A. Ying;Joel Emer;Daniel Sanchez

Year: 2017 | Conference Paper |

Jenga: Software-defined cache hierarchies

Po-An Tsai;Nathan Beckmann;Daniel Sanchez

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA)
Year: 2017 | Conference Paper |
Cited by: Papers (16)
Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range of applications, since working sets settle at the smallest (i.e., fastest and most energy-efficient) level they fit in. However, rigid hierarchies also add overheads, because each level adds latency and energy eve...Show More

Jenga: Software-defined cache hierarchies

Po-An Tsai;Nathan Beckmann;Daniel Sanchez

Year: 2017 | Conference Paper |

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.